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Observer crowleyuk
Registered: ‎04-13-2018

What happens if you give the wrong VCCO for LVDS outputs

Hi there,


I'm looking at a design that interfaces with an 8 Channel ADC from TI.


I the Schematic only connections to the ADC are connected to BANK0, including the clock that drives the ADC.


All inputs are designated LVDS_33, and the one clock out (P/N) is also LVDS_33.


However, the voltage to BANK_0 has been set to 1.8V


I believe this would be OK if the BANK only received LVDS data, as UG381 says any voltage can be applied for LVDS_33 inputs, however am I correct in my thinking that if any LVDS outputs are used there must be 2.5/3.3 V applied to the VCCO?


As you have most likely figured, this design only has 1.8V connected to VCCO. What adverse effects would be expected to be seen?


Best Wishes



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1 Reply
Registered: ‎05-08-2018

Re: What happens if you give the wrong VCCO for LVDS outputs

Will not function properly,


Just that simple.  You must use the correct Vcco for the standard selected.


The only good news here is that LVDS IO on a 3.3v device is compatible with a 2.5v (or even a 1.8v) LVDS device  However, the device Vcco MUST comply with the data sheet (e.g. if the FPGA device IO is LVDS_25, Vcco must be 2.5v).



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