10-26-2010 03:30 AM
I would like to find out what is the default multiboot image load during power-up and crc-error when using Spartan3A_DSP configurating from a SPI flash or Xilinx Platform flash.
For SPI flash, I have read ug332 (Spartan-3 Generation Configuration User Guide) - Chapter 14: Reconfiguration and MultiBoot. On pg275, it stated that "The initial configuration image is always located at address 0, regardless of configuration mode" for power-up. For crc-error, it stated on pg289 that "Set the Reset_on_err:Yes bitstream option to cause the FPGA to automatically re-initialize and retry the first configuration at address 0 should a CRC error occur. Am I right to say that these statements are applicable for SPI and BPI flashes only?
For Xilinx Platform flash, I have read ug161(Platform Flash PROM User Guide) - Chapter 3: XCFxxP Design Revisions. From pg35, it stated that " FPGA is able to configure from revision 1 at power-up and monitor the revision 1 configuration attempt for any failure. In the event of a failure, it then initiates an FPGA reconfiguration from the known-good revision 0." So am I right to say that these statements are applicable for Xilinx Platform flash only? If this is true, how is the default image set? By either internal design revision register in Xilinx Platform flash programmed by IMPACT or explictly setting the external design revision pins of Xilinx Platform flash?
Hope to hear a reply soon. Thanks.
01-11-2011 01:10 AM
For Spartan-3A configuring from a PLatform flash the default image will be configured first. This can be set by the internal revision bits OR the external REV_SEL pins. The Enable External Select pin (EN_EXT_SEL) determines if the external pins or internal bits
are used to select the design revision. For Multiboot with the XCFxxP refer to - http://www.xilinx.com/support/documentation/application_notes/xapp483.pdf
If using Multiboot with Spartan-3A I wouls strongly recommend using an SPI or BPI flah. These are more common solutions.
01-19-2011 10:47 PM
Thank you for your response. I am so glad that someone had responses. Currently, I am exploring with both Xilinx Platform Flash & SPI Flash for multiboot. For Platform Flash, I am following closely the recommended design stated in xapp483. However, I have some doubts on using Platform Flash. They are as follows:
1) Should I configure the fpga as Master or Slave? The application notes seems to draw the CCLK from the fpga to the Platform Flash. However, at the same time, it grounded CSI_B & RDWR_B which is used for Slave Parallel.
2) To receive the user mark (e.g 0x99) from the Platform Flash, do I need to use CCLK to clock the first data out?
3) When using Platform Flash for multibooting, is it possible that I load a default image (e.g. image 1) whenever there is a powerup but reload another image (e..g image 2) whenever there is a configuration of image 1? If not, can I do it with SPI Flash?
Hope to hear from you soon. Thanks.