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Visitor oferst
Visitor
2,737 Views
Registered: ‎05-09-2017

XC3S700AN DCM phase shift overflow behavior

Hello, I designed a module that phase shifts the DCM a variable number of steps. Basically I pulse the PSEN signal for a single PSCLK cycle, waits for the PSDONE pulse and then again pulse PSEN until I reach the number of steps I wanted.
I noticed that in simulation, if I phase shift too much, I end up with roughly 170 steps to positive or negative steps, which at that point STATUS[0] (overflow bit) raises and stays high until I phase shift to the opposite direction, all well and according to specifications.
When I tested my module on hardware however, things were different and not according to specifications. I noticed 2 phenomenons:
1. Overflow bit raised after 380 steps (according to specifications it should raise at most after 255 steps), both in negative and positive directions.
2. In the positive direction, when overflow bit raises, sometimes it stays high but sometimes it vibrates for an indefinite time.

Why could that be?
Help would be much appreciated
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3 Replies
Scholar austin
Scholar
2,724 Views
Registered: ‎02-27-2008

Re: XC3S700AN DCM phase shift overflow behavior

o,

 

Simulation models for complex behaviors may not be accurate.

 

Simply put, the model is intended to show functionality, but is not the actual circuitry.

 

In later families, the models are better, but some are still not perfect (matching exactly actual behavior).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor oferst
Visitor
2,715 Views
Registered: ‎05-09-2017

Re: XC3S700AN DCM phase shift overflow behavior

Thanks for the reply Austin.

 

I understand your point about simulation models.

So does that mean my model can't be truly verified in simulation and my model might have a bug that causes the maximum number of steps that I count to be above 255?

Even if that may be, how come that on hardware the overflow bit sometimes vibrates?

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Scholar austin
Scholar
2,713 Views
Registered: ‎02-27-2008

Re: XC3S700AN DCM phase shift overflow behavior

o,

 

The silicon is what exists, and thus, what you see is real. I would stay within the operating "rules" and not rely on overflow being an exact value (like 255) which it will not be.  Rather, I used a separate counter to mirror the counter in the DCM when I needed to "know" the count, so I could take action.  At least, that is what I did years ago now when I faced a similar issue.

Austin Lesea
Principal Engineer
Xilinx San Jose
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