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Visitor sns2203
Visitor
5,039 Views
Registered: ‎09-19-2016

XC6SLX45T-CSG324 Power Issue

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Hi,

 

I have a problem regarding the powering of one bank with Vcco = 3.3V. The other vcco are connected to 1.2V and 2.5V. 

I am programming the FPGA using a bit file through JTAG lines. When the Vcco = 3.3V the FPGA fails to program but when

I increased the voltage to 3.4V the FPGA could be programmed with the current consumption of 840mA.

 

The strange phenomena is that we have 4 identical boards and 2 of them are able to be programmed with Vcco=3.3V but have a higher current consumption of 940mA while other 2 boards can only be programmed with 3.4V (840mA) and fail at 3.3V. All tests were done in identical power and cables setup. The boards are identical in design & routing. They have some capacitors, a passive sensor and an FPGA.

 

My initial idea was maybe there is timing failure between the JTAG TCK clock and data line TDI during the programming cycle. So I checked it for tsu setup time and thold time failures with scope during the programming cycle. I didn't find any such failure in the results.

 

Can anyone tell me how to start debugging this problem? I am at a loss of the ideas. 

Should I check TDO line with the TCK for any anomalities?

 

Cheers,

Sns

 

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Xilinx Employee
Xilinx Employee
8,980 Views
Registered: ‎08-01-2012

Re: XC6SLX45T-CSG324 Power Issue

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@sns2203 Glad to know that it is working now

 

Decoupling capacitors help to minimize noise due to fast IO switching. Also little extent help to avoid drop in voltage if regulator is slow react. But always the best solution is using suitable regulator or power supply as per power requirement.  

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Scholar austin
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Registered: ‎02-27-2008

Re: XC6SLX45T-CSG324 Power Issue

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sns,

 

Strange - does not make sense.  What is the Vccint voltage?  What is the Vccaux voltage?  Is the part hot?  How hot?  What is the Vcco voltage at the part, on the board?  Are the wires you are using thick enough to carry the current (without a drop)?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Xilinx Employee
Xilinx Employee
4,990 Views
Registered: ‎08-01-2012

Re: XC6SLX45T-CSG324 Power Issue

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@sns2203 - mentioned that I have a problem regarding the powering of one bank with Vcco = 3.3V. The other vcco are connected to 1.2V and 2.5V. I am programming the FPGA using a bit file through JTAG lines. When the Vcco = 3.3V the FPGA fails to program but when increased the voltage to 3.4V the FPGA could be programmed with the current consumption of 840mA.

 

Based on your inputs I am suspecting that your 3.3V power supply/regulator is not supporting enough load. Please try to follow below suggested steps as much as possible for you

 1. Use proper decoupling recommendations as per Spartan-6 PCB design user guide

  1. Scope the 3.3V poser supply rail nearest test point to the FPGA and check for noise in 3.3V rail. If any SI issue  fix it
  2. If still problem exists then try to replace (if possibilty exists) your board 3.3V regulator/supply with higher load specification regulator/supply
________________________________________________

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Visitor sns2203
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Registered: ‎09-19-2016

Re: XC6SLX45T-CSG324 Power Issue

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Hi Austin,

 

Yes, its very strage behaviour and has cost me a week.

 

Vccint voltage = 1.2V with decoupling capacitors.

VCCAUX   = 2.5V

VCCO = 2.5V, 1.2V and 3.3V

 

A passive sensor sits close to the FPGA has measured a maximum of 69 deg C. 

I have also found out that the FPGA can be programmed from the xilinx debugger & chipscope 

but fails when we try to program via JTAG lines.

 

In another post I saw here,

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/spartan6-fpga-Jtag-connection-issue/td-p/119514/page/2

 

where it states that INIT_B should be pulled HIGH but in my design it is a floating pin. Can this be a reason?

Although PROGRAM_B pin is pulled high to 2.5V.

 

I think some signal (maybe clk) is at the edge @3.3V and when the voltage is increased to 3.4V, the FPGA becomes faster and removes this issue but I don't know which signal it is. Can it be this?

 

Can it be that my clock to progam the FPGA is too fast?

 

Cheers

Karin

 

 

 

 

 

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: XC6SLX45T-CSG324 Power Issue

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Yes,

 

INIT_b must be pulled high.

 

69 C outside the device is well in excess of 85 C junction temperature -- it is likely you are outside of the recommended device operating temperature (85 C max, commercial).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor sns2203
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4,976 Views
Registered: ‎09-19-2016

Re: XC6SLX45T-CSG324 Power Issue

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Hi,

 

I have another question. The FPGA is drawing 1 Amp current and it seems we have not put in enough

decoupling capacitors in the 3.3V power line.

I have checked in the http://www.xilinx.com/support/documentation/user_guides/ug393.pdf

where a minimum number of 4.7uF 0.47uF and 100 uF capacitors are recommended but not with respect to the

current consumption of the device. How to calculate that?

 

 Is INIT_b pulled HIGH internally? Is was left floating in the PCB? What will happen if INIT_b is left floating? Can we expect some failures?

 

Cheers

Karin 

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Visitor sns2203
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4,928 Views
Registered: ‎09-19-2016

Re: XC6SLX45T-CSG324 Power Issue

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Hi All,

 

@umamahe 

 

 1. Use proper decoupling recommendations as per Spartan-6 PCB design user guide

     We followed the recommendations for the Spartan 6 guide specially related to decoupling capacitors. But our current                   consumption is too high @1Amp &  it seems the capacitors were not enough. 

 

  1. Scope the 3.3V poser supply rail nearest test point to the FPGA and check for noise in 3.3V rail. If any SI issue  fix it

     You are right the problems seems to have been a sudden dip in the 3.3V line to 2.5V just after the programming cycle ends        and the FPGA tries to draw 1A current. This voltage regulator was too slow to meet this requirement. And at the point the            voltage reaches 2.5V the FPGA shuts down.

 

3. If still problem exists then try to replace (if possibilty exists) your board 3.3V regulator/supply with higher load specification regulator/supply

 

After increasing the regulator speed the boards work with good voltage tolerance.

 

Some Experimental Observations:

 

I also found out that with the other 2 boards which were working before were also at the edge of the 3.3V. And although this dip in voltage can be seen (also in the previous working boards) in the 3.3V line it wasn't so low but around 2.8V and the FPGA could draw the 1A current (which other defekt boards weren't able to) . But if the supply voltage is set to 3.2V the functional boards also stopped working as this dip in the voltage line was close to 2.5V and the FPGA thinks that the power has been switched off in this moment. 

 

Now with the increased speed of the 3.3V voltage regulator line this short dip has disappeared and the FPGA is quickly able to draw 1A current from the regulator.

 

But I would we were lucky to find this balance. As the voltage regulator in the Power supply has only 3 settings. And if we make it too fast the 3.3V line starts ringing. But now we have a good compromise that the regulator is not too fast enough for the voltage line to ring and not too slow enough (so it can still provide 1A current quickly).

 

Do you think this problem can be solved by say adding more capacitors close to the power line and of higher values say 1000 uF or so?

I have also seen that the current consumption of the line has changed now. Previously for 3.3V it was @934mA (slow regulator) but now with faster regulator speed it is 3.3V @884mA . Do you have any explanation to this?

 

Cheers

 

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Xilinx Employee
Xilinx Employee
8,981 Views
Registered: ‎08-01-2012

Re: XC6SLX45T-CSG324 Power Issue

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@sns2203 Glad to know that it is working now

 

Decoupling capacitors help to minimize noise due to fast IO switching. Also little extent help to avoid drop in voltage if regulator is slow react. But always the best solution is using suitable regulator or power supply as per power requirement.  

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

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