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Xilinx Employee
Xilinx Employee
41,719 Views
Registered: ‎03-09-2011

Xilinx® Training on Spartan Family FPGAs

Designing with the Spartan-6 and Virtex-6 FPGA Families - Updated March 2011

Are you interested in learning how to effectively utilize Spartan-6 FPGA or Virtex-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families. - Test Your Knowledge

 

Play Video Spartan-6 Memory Resources
Learn how to fully utilize the Spartan®-6 distributed and block memory resources, understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB), use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component.

Updated: Sept 2012
Play Video Spartan-6 Slice and I/O Resources
Learn how to describe the basic slice and I/O resources available in Spartan-6 FPGAs.

Updated: Sept 2012
Play Video Spartan-6 Clocking Resources
Learn how to describe the global and I/O clock networks in the Spartan-6 FPGA, describe the clock buffers and their relationships to the I/O resources, describe the DCM capabilities in the Spartan-6 FPGA.

Updated: Sept 2012
Play Video Virtex-6 & Spartan-6 FPGA HDL Coding Techniques
Learn how to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources, code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR).

Updated: Sept 2012
Play Video Spartan-3 FPGA HDL Coding Techniques
Learn how to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. code properly for carry logic and memory resources. You will also know how to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs.

Updated: Sept 2012

 

Essentials of FPGA Design - Updated Oct 2013

Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.

 

Designing for Performance - Updated June 2012

Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs. - Test Your Knowledge

 

Advanced FPGA Implementation - Updated June 2012

Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE design suite and Xilinx hardware. Labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and 7 series FPGAs. - Test Your Knowledge

 

FPGA Design Techniques for Lower Cost

This course appeals to engineers who have an interest in developing low-cost products, particularly in high-volume markets. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.

7 Replies
Newbie shakeel
Newbie
40,553 Views
Registered: ‎09-10-2011

Re: Xilinx® Training on Spartan Family FPGAs

please help me to connect RC SERVO Motor with Spartan 3E

i have a Verilog Code of it just want to know about how spartan 3E connect with RC Servo Motor

 

0 Kudos
39,436 Views
Registered: ‎03-27-2012

Re: Xilinx® Training on Spartan Family FPGAs

I just want to say thank you for providing this information for new users. My client wants me to browse and look for information that we can possible use in the future.

 

Tags (1)
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Visitor echo083
Visitor
33,977 Views
Registered: ‎07-30-2013

Re: Xilinx® Training on Spartan Family FPGAs

Wonderful videos :) You even provide powerpoints. Thanks for all this nice work !!!

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Visitor gannicus
Visitor
32,698 Views
Registered: ‎12-12-2013

MH/s oder GH/s

Hello,

 

which product of xilinx has a computing power of 10 GH / s or more?

 

 

Thank You

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Explorer
Explorer
32,281 Views
Registered: ‎09-23-2011

Re: MH/s oder GH/s

Any such videos for MGTs/GTP_duals ?

 

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Visitor gwzlmmt
Visitor
29,243 Views
Registered: ‎12-08-2013

Re: Xilinx® Training on Spartan Family FPGAs

Tanks verymuch
Tags (1)
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Visitor songyuntao
Visitor
13,183 Views
Registered: ‎03-02-2017

Re: Xilinx® Training on Spartan Family FPGAs

Excuse me, I have a problem with the simulation.

I have done the systhesis and implementation successfully but the post simulation have a problem.

The behavior simulation is right, but the two post timing simulation show the same output with the bahavior simulation. In face, it should have the time delay but the output doesnt show this.

I dont know where the problem is and I hope you may help me.

The attahment is one of the test file I use.

I hope to hear you soon.

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