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Visitor
Visitor
22,673 Views
Registered: ‎09-17-2007

activate clk

hi guys!

I have a spartan-3e and I am trying to activate the clock in order to give Pulses
repeatedly. I have read the manual and some examples but something it is going wrong.

Could you advise me please?

I use the software from Xilinx ISE 8.2i

Thank you in advance!!!

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Xilinx Employee
Xilinx Employee
22,670 Views
Registered: ‎08-13-2007

Antonios,
 
Can you please clarify what you mean by "trying to activate the clock"?
 
It isn't clear if you are referencing:
-enabling an external oscillator
-trying to use a DCM for clock distribution (e.g. IBUFG -> DCM -> BUFG)
-using an internal clock gating circuit for internal or external clock distribution
-other technique
 
Does "give pulses repeatedly" mean to produce a free-running clock (e.g. 50Mhz) or something else?
 
What are you trying to do and what do you see?
 
Cheers,
bt
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Visitor
Visitor
22,661 Views
Registered: ‎09-17-2007

Dear Barrie,

1st:  I would like to thank you because you want to help me.
2nd : I really sorry for my bad English.

I think I
mean to produce a free-running clock.

I am trying to do a counter.
this is the  code that I use (taken from the Help)  :

entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0);
begin

process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;

my .ucf file is :
     CLOCK    Input    C9    BANK0    LVCMOS33    N/A    3.30                   
     COUNT_OUT<0>    Output    f12    BANK0    LVTTL    N/A    3.30    8        SLOW       
     COUNT_OUT<1>    Output    e12    BANK0    LVTTL    N/A    3.30    8        SLOW      
     COUNT_OUT<2>    Output    e11    BANK0    LVTTL    N/A    3.30    8        SLOW      
     COUNT_OUT<3>    Output    f11    BANK0    LVTTL    N/A    3.30    8        SLOW        Unknown        0
     DIRECTION    Input    l13    BANK1    LVTTL    N/A    3.30        PULLUP           

I expect to see the led  flashing depending on the clock but I see the four led permanently turning on.

Thank you in advance,
Antonis
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Explorer
Explorer
22,635 Views
Registered: ‎08-30-2007


Hello Antonis…

I don’t know if this will solve your problem but it is a good coding practice and very important to reset your counter first.

Use the code below
--------------------------------------------------------------

LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY counter16 IS
  PORT (
      clk       : IN  std_logic;
      rst_n     : IN  std_logic;
      DIRECTION : IN  std_logic;
      counter   : OUT std_logic_vector (3 DOWNTO 0));
END counter16;

ARCHITECTURE rtl OF counter16 IS

  SIGNAL counter_int : std_logic_vector(3 DOWNTO 0);

BEGIN
  PROCESS(clk, rst_n)
  BEGIN
    IF rst_n = '0' THEN
      counter_int   <= "0000";
    ELSIF rising_edge(clk) THEN
      IF DIRECTION = '1' THEN
        counter_int <= counter_int + 1;
      ELSE
        counter_int <= counter_int - 1;
      END IF;
    END IF;
  END PROCESS;
  counter           <= counter_int;
END;
-----------------------------------------------------------

If you can not use an external reset signal just initialize the internal counter signal ….

------------------------------------------------------------

ENTITY counter16 IS
  PORT (
      clk       : IN  std_logic;
      DIRECTION : IN  std_logic;
      counter   : OUT std_logic_vector (3 DOWNTO 0));
END counter16;

ARCHITECTURE rtl OF counter16 IS

  SIGNAL counter_int : std_logic_vector(3 DOWNTO 0) := "0000";

BEGIN
  PROCESS(clk)
  BEGIN
    IF rising_edge(clk) THEN
      IF DIRECTION = '1' THEN
        counter_int <= counter_int + 1;
      ELSE
        counter_int <= counter_int - 1;
      END IF;
    END IF;
  END PROCESS;
  counter           <= counter_int;
END;

----------------------------------------------------------

Another thing that I must note is that if this works, the LEDs might change their state very quickly for you to see. This depends also on the clock frequency ....


George


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Visitor
Visitor
22,626 Views
Registered: ‎09-17-2007

 Geia xara George,

Thank you very much for your help.

I had  written  like your code and the results were the same.

You should have right about the speed, but how can I fix  the frequency?

Antonis
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Professor
Professor
22,600 Views
Registered: ‎08-14-2007

You didn't mention which board you are using, but in any case the on-board clocks are usually in the 50 MHz range.  In order to see LED's blink you need to be in the range of 10 Hz (not MHz) or less.  A simple way to slow the clock down is to use a long counter, maybe 24 bits, and use its carry out as a clock enable for your up-down counter.  Another way is to just increase the number of bits in your up down counter, say to 28 bits, and assign only the 4 most significant bits to LED's.

HTH,
Gabor
-- Gabor
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Visitor
Visitor
22,593 Views
Registered: ‎09-17-2007

hi Gabor,

I am using spartan-3e board.

Is there any way to change the freequency from my clock?


Thanks,

Antonis
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Xilinx Employee
Xilinx Employee
22,586 Views
Registered: ‎08-13-2007

Antonis,
 
As Gabor suggested, your outputs are currently much too fast for your eyes to see. It looks like they are constantly on, but they are actually being modulated at a rate of 25Mhz, 12.5Mhz, 6.25Mhz, and 3.125Mhz as the S3ESK has a 50MHz oscillator on the C9 input. You certainly don't want to have to change the oscillator - I haven't seen an oscillator in the <10Hz range, though perhaps they do exist. Luckily, it is quite easy to change the logic to implement something that would be visible to the human eye as Gabor mentioned
 
As as example, change 2 of your lines of code
FROM:
signal count_int : std_logic_vector(3 downto 0);
TO:
signal count_int : std_logic_vector(29 downto 0);  -- increasing the length of the counter for a progressive reduction of half the frequency per each additional bit
 
FROM:
COUNT_OUT <= count_int;
TO:
COUNT_OUT <= count_int(count_int'left downto count_int'left - 3);  -- this takes the most significant 4 bits of the internal counter
 
Too few bits and your eyes won't keep up (but a scope would reveal the rate). Too many bits and you will be waiting awhile. ;)
 
Now you'll have a simple up/down binary counter with sufficient resolution that you should be able to see visibly. A good start for a "hello world" design.
There are many other types of counters you could use, including T FF cascade to next FF CE, additional counter prescalar, loadable threshold for terminal count, NCO, etc. They will have trade-offs in their complexity, resolution, flexiblity, etc.
 
You can also play games with the duty cycle of the output to pulse width modulate the intensity of the LED. But this should be good start.
 
Good luck and have fun.
 
Cheers,
bt
 
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Visitor
Visitor
22,581 Views
Registered: ‎09-17-2007

timpe ,Gabor ,George

:D

I don't have words in order to thank you  for you real help guys!!!



T h a n k    y o u!!!!!
Antonis

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Visitor
Visitor
22,580 Views
Registered: ‎09-17-2007

also,

Could you suggest me a Vhdl Book?

Thank you
Antonis
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Xilinx Employee
Xilinx Employee
8,819 Views
Registered: ‎08-13-2007

Antonis,
 
Welcome to the world of FPGA design. ;)
 
I don't have any specific books (maybe others can chime in here), but if you do look for one, I would recommend that you find one specifically focused on hardware synthesis. VHDL (and other HDLs such as Verilog) allows you to do many things in simulation, but you really want a reference than focuses on synthesizable hardware - ideally FPGAs. ;) Although non-synthesizable constructs can certainly be useful for simulation testbenches.
 
Here are a few Xilinx resources you may find useful:
http://www.xilinx.com/bvdocs/appnotes/xapp105.pdf (XAPP105 - A CPLD VHDL Introduction)
http://www.xilinx.com/bvdocs/appnotes/xapp215.pdf (XAPP215 - Design Tips for HDL Implementation of Arithmetic Functions), dated but still useful
http://www.xilinx.com/products/silicon_solutions/cplds/resources/coolvhdlq.htm (CPLD File Set Downloads)
 
We also have many app notes - often with source code available:
Here are a few other resources I have found useful for one reason or another:
http://www.mlab.ice.uec.ac.jp/mit/text/JyoTsuEnsyu/2005/VHDL_Language_Reference.pdf (VHDL Language Reference)
http://www.synthworks.com/papers/index.htm (SynthWorks' VHDL Papers)
http://www.hardi.com/haps/literature/VHDL-Handbook.pdf (HARDI VHDL handbook)
[note: this is not an official Xilinx recommendation here - just a few personal suggestions.] I am sure there are many others out there as well.
 
 
Best of luck,
bt
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Visitor
Visitor
8,814 Views
Registered: ‎09-17-2007

timpe,

Thank you very much about everything. You are very kind and i really appreciate it.


Best regards,

Antonis

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