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Observer
Observer
6,513 Views
Registered: ‎09-25-2014

an question about memory controler of SPARTAN6

 

 

   Anyone could give me some suggestion?Pls help me.   

In the Table 2-4 of the UG 388,there mentioned an signal which name is"mcb_drp_clk", but when I using the core gen,I could not find this signal,and the IP generated by core gen had another signal,"c1_sys_clk".What is the relationship between this two signals?And I could not found the pll_ce_0,pll_ce_90,pll_lock,sysclk_2x,sysclk_2x_180 also,which listed in the same table.

    Btw,my design tool is ISE14.7,mig in the core gen is version 3.92, and the UG388 is (v2.3) August 9, 2010.And my chip is LX45-fgg676

 

 

Thanks a lot for any suggestion

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Explorer
Explorer
6,021 Views
Registered: ‎05-31-2015

Re: an question about memory controler of SPARTAN6

Hello,

 

    You can refer to the example generated by the memory controller for more information... May help you.

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