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Visitor centu002
Visitor
7,193 Views
Registered: ‎02-09-2011

big problem with core generator

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Hello

For next code I must create a ROM with Core generator  (FIFO Generator3.2)(I use Spartan3E), but I can not mark "Build-in FIFO". If someone   can help me.

 

1)--FIFO

signal               din:  std_logic_VECTOR(11 downto 0);

signal rd_en: std_logic;

signal wr_en: std_logic;

signal dout: std_logic_VECTOR(11 downto 0);

--signal             empty: std_logic;

--signal             full: std_logic;

signal   FIFO_output : std_logic_vector (11 downto 0);

 

2)-- FIFO

ADCFIFO: FIFO

            port map (

            clk=> CLK,

            din=> DATA,

            rd_en => START,--pushbutton BTN_West

            rst=> RST,

            wr_en=>DONE,

            dout=> FIFO_output,--LED, LCD ROM

            empty=> open,

            full=> open);

 

 

 

xilinx forum.JPG
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Teacher eteam00
Teacher
9,256 Views
Registered: ‎07-21-2009

Re: big problem with core generator

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I must create a ROM with Core generator  (FIFO Generator3.2)(I use Spartan3E), but I can not mark "Build-in FIFO".

Spartan-3e does not have built-in FIFO blocks.  The FIFO block built from Block RAM (BRAM) should be mostly equivalent to a hardware FIFO block.  Note (3) in the FIFO Generator dialogue (shown in your post) clearly references Virtex 4 and Virtex 5 built-in FIFO primitives.  Note(3) is marked in the supported features column, next to the Built-In FIFO option.

 

If you read DS317 (see Table 7), it describes that only certain FPGA families include built-in FIFO blocks:

  • Virtex 4, 5, 6, 7
  • Kintex-7

FIFO generator is at version 8.1, you are using an ancient version of the software.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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View solution in original post

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Teacher eteam00
Teacher
9,257 Views
Registered: ‎07-21-2009

Re: big problem with core generator

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I must create a ROM with Core generator  (FIFO Generator3.2)(I use Spartan3E), but I can not mark "Build-in FIFO".

Spartan-3e does not have built-in FIFO blocks.  The FIFO block built from Block RAM (BRAM) should be mostly equivalent to a hardware FIFO block.  Note (3) in the FIFO Generator dialogue (shown in your post) clearly references Virtex 4 and Virtex 5 built-in FIFO primitives.  Note(3) is marked in the supported features column, next to the Built-In FIFO option.

 

If you read DS317 (see Table 7), it describes that only certain FPGA families include built-in FIFO blocks:

  • Virtex 4, 5, 6, 7
  • Kintex-7

FIFO generator is at version 8.1, you are using an ancient version of the software.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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Visitor centu002
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Registered: ‎02-09-2011

Re: big problem with core generator

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So I have to keep some bits in memory and then have to throw on an LCD.
What advice would you give me?

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Teacher eteam00
Teacher
7,159 Views
Registered: ‎07-21-2009

many ways to build a FIFO

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So I have to keep some bits in memory

Well, a built-in FIFO is considered memory (dedicated purpose memory), right?  In the case of Spartan-3e, you would be using general purpose memory (Block RAM) for FIFO.  Use the core generator option which is appropriate for Spartan-3e.  That's what everyone else does, with no complaints to speak of.

and then have to throw on an LCD.

Please explain.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor centu002
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7,148 Views
Registered: ‎02-09-2011

Re: many ways to build a FIFO

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I attached a block diagram of what I want to do. And I use an Nexys 2 500k board.

I want to know if it works or not with this board and if it works, what version of core gen i must use.

 

Thanks for the advice.

FORUM.jpg
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Teacher eteam00
Teacher
7,145 Views
Registered: ‎07-21-2009

Re: many ways to build a FIFO

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I attached a block diagram of what I want to do. And I use an Nexys 2 500k board.

Your block diagram does not reference a FIFO, and it doesn't need to reference a FIFO.

The development board uses a Spartan-3e FPGA

I want to know if it works or not with this board and if it works, what version of core gen i must use.

Any version of coregen which supports Spartan-3e should work.  If you are running Windows Vista or Windows 7, and you are having trouble with running the tools, then you should consider updating your ISE tools software.

 

The only problem you seem to have is which option to select in the coregen wizard for FIFO generation.  You must choose one of the options which is supported by Spartan-3e.  If you select one of those options, you should have no problems going forward.

 

The available and supported option which most closely resembles the 'built-in FIFO' option (which is not supported in Spartan-3e) is Block RAM.  Try the Block RAM option, it should work well for your purposes.

 

You will need to choose between common clock and independent clocks, based on the requirements of your design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor centu002
Visitor
7,113 Views
Registered: ‎02-09-2011

Re: many ways to build a FIFO

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With the memory I think I solved (I must use Distributed Memory Generator whitch is compatible with my Nexys 2 board. Also I download the last version of ISE 13.1)

All good up here.

 

Next issue is:

 

I must creat a *.coe file what  contain this chart data

 


dB Values

LED code (“1” ON, “0” OFF)

Reset or No Reading

00000000

-70 (including -80)

10000000

-60

11000000

-50

11100000

-40

11110000

-30

11111000

-20

11111100

-10

11111110

0

11111111

I appreciate any suggestions. Thanks.
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Scholar joelby
Scholar
7,098 Views
Registered: ‎10-05-2010

Re: many ways to build a FIFO

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Wouldn't it be simpler to have a nice, big nested if statement? (or some pipelined subtractors and a case statement, or something). You *could* do the lookup with RAM, but it seems like a long-winded way to do it.

 

The coe file format is very straightforward - see http://www.xilinx.com/itp/xilinx4/data/docs/cgn/ch3-using20.html .

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Visitor centu002
Visitor
7,072 Views
Registered: ‎02-09-2011

Re: many ways to build a FIFO

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With coe file I do. But now I have other problem. I dont understand what is wrong in this part of code: attached file I comment the error

 

 

 

 

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Scholar joelby
Scholar
7,070 Views
Registered: ‎10-05-2010

Re: many ways to build a FIFO

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You're in luck - these error messages are very self-explanatory.

 

--User interface signals
	DATA => DATA
	START => START,--pushbutton BTN_0-----------------------------------------here I reciv an error(Line 65. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR)
	DONE => DONE);

 You're missing a comma after "DATA"

 

LEDROM : LED_DISTMEM
			port map (
			a => DATA
			spo => LED_ROM_OUTPUT);-----------------------------------and here some like first error(Line 71. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR)

 Again, you're missing a comma after DATA.

 

Visitor centu002
Visitor
6,897 Views
Registered: ‎02-09-2011

Re: many ways to build a FIFO

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O yea, I'm kind of distraught. Thank you very much.

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Visitor centu002
Visitor
6,882 Views
Registered: ‎02-09-2011

Re: many ways to build a FIFO

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A simple question: It is possible to make this without a precalculated value in a ROM?

 

I want to send the 8 bits from the converter output to the 8 leds on the board some like this

 

when data conversion from and audio signal is   "10000000" turn on led 0

"11000000" turn on led 1 and keep led 0 on

"11100000" turn on led 2 and keep led 0 and 1 on

.

.

.

"11111111" turn on led 7 and keep on led 0,1,2,3,4,5,6

I use Nexys 2-500k board and a PmodAD1 AD7476 chips.

 

I wait your opinions and possibly a start code

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Scholar joelby
Scholar
6,873 Views
Registered: ‎10-05-2010

Re: many ways to build a FIFO

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For the scenario you've listed, you can just do

 

assign leds[7:0] = converter_output[7:0];

However this may light LEDs in reverse order. It'll probably be easiest to redefine the ports in your UCF file in reverse order, or do

 

assign leds[7:0] = {converter_output[0], converter_output[1], converter_output[2], ...};

I suspect you're asking the wrong question, though. What do you want to display if the 8-bit converter shows 10101010? Do you just want to display the exact value on the LEDs, or do really mean to do something like the following (in pseudo-code)?

 

if (converter_output < 16)
  leds <= 8'b00000000;
if (converter_output < 32)
  leds <= 8'b10000000;
if (converter_output < 48)
  leds <= 8'b01000000;
if (converter_output < 64)
  leds <= 8'b00100000;

etc.

 

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Visitor centu002
Visitor
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Registered: ‎02-09-2011

Re: many ways to build a FIFO

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I want to put a condition. Something like: if data out (from PmodAD1) = "11111111" turn on led 8. And other data "10101010" must ignored.

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Scholar joelby
Scholar
6,867 Views
Registered: ‎10-05-2010

Re: many ways to build a FIFO

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In that case, a case statement with an appropriate default condition should be all you need.
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Visitor centu002
Visitor
6,858 Views
Registered: ‎02-09-2011

Re: many ways to build a FIFO

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I did it with ROM but i reciv a warning   " WARNING:Xst:2211 - "C:/Users/Audiometer_toplevel.vhdl" line 73: Instantiating black box module <LED_DISTMEM>."

 when I click on this warning it send me to this code:

 

LEDROM : LED_DISTMEM

port map (

a => DATA1, 

CLK => CLK,

spo => LED_ROM_OUTPUT );

 

 

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Teacher rcingham
Teacher
6,856 Views
Registered: ‎09-09-2010

Re: many ways to build a FIFO

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If the LED_DISTMEM is defined as an .NCG file or similar, XST will not find it, but the Mapper will. Have you run the Mapper? If not, run the Mapper, and Place&Route, and see whether a correctly sized RAM-as-ROM is incorporated.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor centu002
Visitor
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Registered: ‎02-09-2011

Re: many ways to build a FIFO

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Yes is a file LED_DISTMEM.ngc (not .ncg) and in Map Report I have some 
Release 13.1 Map O.40d (nt64)
Xilinx Mapping Report File for Design 'Audiometer_toplevel'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off
-c 100 -o Audiometer_toplevel_map.ncd Audiometer_toplevel.ngd
Audiometer_toplevel.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -5
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date    : Wed Jun 29 12:01:30 2011

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:            66 out of   9,312    1%
  Number of 4 input LUTs:                21 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:             39 out of   4,656    1%
    Number of Slices containing only related logic:      39 out of      39 100%
    Number of Slices containing unrelated logic:          0 out of      39   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:          21 out of   9,312    1%
  Number of bonded IOBs:                 23 out of     232    9%
  Number of BUFGMUXs:                     2 out of      24    8%

Average Fanout of Non-Clock Nets:                2.64

Peak Memory Usage:  230 MB
Total REAL time to MAP completion:  7 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network LEDROM/N1 has no load.
INFO:LIT:395 - The above info message is repeated 1 more times for the following
   (max. 5 shown):
   LEDROM/N0
   To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   1 block(s) optimized away
   2 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "LEDROM/N1" is sourceless and has been removed.
The signal "LEDROM/N0" is sourceless and has been removed.
Unused block "LEDROM/GND" (ZERO) removed.
Unused block "LEDROM/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		LEDROM/BU2/XST_GND

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| CLK                                | IBUF             | INPUT     | LVCMOS25             |       |          |      |              |          | 0 / 0    |
| DATA2<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| DATA2<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<0>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<1>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<2>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<3>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<4>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<5>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<6>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| LED<7>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| RST                                | IBUF             | INPUT     | LVCMOS25             |       |          |      |              |          | 0 / 0    |
| SCLK                               | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
| SDATA1                             | IBUF             | INPUT     | LVCMOS25             |       |          |      |              |          | 0 / 0    |
| SDATA2                             | IBUF             | INPUT     | LVCMOS25             |       |          |      |              |          | 0 / 0    |
| START                              | IBUF             | INPUT     | LVCMOS25             |       |          |      |              |          | 0 / 0    |
| nCS                                | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          | 0 / 0    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
This design was not run using timing mode.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.

 but I do not understand what is wrong or if is wrong

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Teacher rcingham
Teacher
6,844 Views
Registered: ‎09-09-2010

Re: many ways to build a FIFO

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If you are running the tools through ISE, you probably have to add LED_DISTMEM.xco or LED_DISTMEM.ngc to the project.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor centu002
Visitor
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Registered: ‎02-09-2011

Re: many ways to build a FIFO

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Something goes wrong and and I think it is because I put wrong numbers in the .coe file.

I have to put 12bits data in input and 8bits data to output

 

So I  created a distributed memory rom with 12 bits data input a[11:0] and 8bits data out spo[7:0]  and my .coe data is this:

Sample memory initialization file for Distributed Memory v2.0 and ; later.; ; This .COE file is NOT compatible with v1.0 of Distributed Memory Core.; ; The example specifies initialization values for a memory of depth= 4096, ; and width=8. In this case, values are specified in hexadecimal format.
memory_initialization_radix = 16

;memory_initialization_vector =

FFmust be 00000000

FE10000000

FC11000000

F811100000

F011110000

E011111000

C011111100

8011111110

00;11111111 I take only the 8 MSB from 12bits data input 

 

 

dB Values

LED code (“1” ON, “0” OFF)

Reset or No Reading

00000000

-70 (including -80)

10000000

-60

11000000

-50

11100000

-40

11110000

-30

11111000

-20

11111100

-10

11111110

0

11111111

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Scholar joelby
Scholar
2,092 Views
Registered: ‎10-05-2010

Re: many ways to build a FIFO

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The COE file is supposed to contain a value for every memory location. You've specified a 4096 byte RAM and only given nine memory locations. Unless you're scaling your input (the ADC's output) to within the range 0-9, you'll probably get an all zero output.

 

I do understand what you're trying to do, and believe me - RAM is really one of most convoluted ways you could do it.

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