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iceinsky
Observer
Observer
4,829 Views
Registered: ‎11-23-2010

constraint about LVDS ports

Hi, i have a disign in lx150 in spartan family , there are some LVDS ports used on the pins of chips,i have read the datasheet of constaint about lvds,but i have not got a example about  how to add constaint to source synchronous signals ,so that i wil show my ports , and need some help about how to add a good constraint

 

there 3 pairs in the port ,including 2 pairs of clock lines and one pair of data lines ,.one frame  synchronous clock  which is 50MHz, one data captured clokc which is 300 MHz. also the data lines 300MHz ,

 

the data lines and frame synchronous  clocck are synchronous  with the same phase , the data captured clock hava a 0.83ns delay after them.

 

so could you show me how to add constaint to  them.

 

that is all, thanks

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4 Replies
iceinsky
Observer
Observer
4,804 Views
Registered: ‎11-23-2010

Does anybody kown how to add a constraint to lvds source synchronous input ?

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ywu
Xilinx Employee
Xilinx Employee
4,777 Views
Registered: ‎11-28-2007

I assume you're asking about the offset in constraints for the interface. It's the same for LVDS source synchronous interface as any other interface. You can take a look at the blog below for some examples:

 

http://myfpgablog.blogspot.com/2009/09/offset-in-constraints-on-diff-inputs.html

 

Cheers,
Jim
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pml
Visitor
Visitor
4,757 Views
Registered: ‎10-23-2010

Hello Jim,

 

From the link :

 

 

" When the OFFSET IN constraints are specified with input nets,  they are simply ignored by the timing analyzer in ISE 11.3 (see UCF constraints and TA snapshot below):
This is probably caused by a bug in TA. As a workaround, the OFFSET IN constraints can be also specified with TIMEGRP and the tool will correctly analyze the timing constraint (see the UCF constraints and TA snapshot below)"

 

I guess this has been fixed with latest version of ISE ?

 

Thanks.

Philippe.

 

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ywu
Xilinx Employee
Xilinx Employee
4,737 Views
Registered: ‎11-28-2007

Thanks for the follow-up. Just verified in IDS 12.4 the bug has been fixed. I also updated the blog. I should have done this earlier, but it's better late than never.

 

 


@pml wrote:

Hello Jim,

 

From the link :

 

 

" When the OFFSET IN constraints are specified with input nets,  they are simply ignored by the timing analyzer in ISE 11.3 (see UCF constraints and TA snapshot below):
This is probably caused by a bug in TA. As a workaround, the OFFSET IN constraints can be also specified with TIMEGRP and the tool will correctly analyze the timing constraint (see the UCF constraints and TA snapshot below)"

 

I guess this has been fixed with latest version of ISE ?

 

Thanks.

Philippe.

 


 

Cheers,
Jim