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sha@hys
Explorer
Explorer
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Registered: ‎05-31-2015

fixed point operation in VHDL unexpected result

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Hello,

        I am implementing fixed point operations in VHDL. I tried to multiply 131 (signal c4:sfixed(7 downto -1):="100000110";) with 1.5 (signal c3:sfixed(1 downto -1):="011";). The expected result is 196.5 (c5:sfixed(9 downto -2)=001100010010) , but I am getting c5[9:-2]=110100010010 in simulation. It is basically PID code , but issue is regarding c5<=c3*c4 part only as I said. Code is given below...Why do this happen? How can I prevent it from happening?

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;

 

entity pidtest is
port(
clk : in std_logic;
--pid_input0 : in sfixed(7 downto -6):="00000001100000";
pid_input0 : in sfixed(7 downto -6):="00000001000000";
--pid_input1 : in sfixed(7 downto -6);
--pid_input1: in sfixed(7downto -6);
p_gain : in sfixed(7 downto -6):="00000000011000";
i_gain : in sfixed(7 downto -6):="00000000011000";
d_gain : in sfixed(7 downto -6):="00000000011000";
output1: out sfixed(19 downto -12);
outputslv : out std_logic_vector (31 downto 0));
end pidtest;

 

architecture Behavioral of pidtest is

signal previousOutput_DispCtrl : sfixed(7 downto -6):=(others=>'0');
signal junk : sfixed(7 downto -6):=(others=>'0');
signal junk2 : sfixed(7 downto -6):=(others=>'0');
signal previousError_DispCtrl : sfixed(7 downto -6):=(others=>'0');
signal pid_error:sfixed(8 downto -6):=(others=>'0');
signal pid_input1:sfixed(7 downto -6):=(others=>'0');
signal output:sfixed(19 downto -12):=(others=>'0');
signal output2:sfixed(7 downto -6):=(others=>'0');
signal output3:sfixed(19 downto -12):=(others=>'0');
signal output4:sfixed(19 downto -12):=(others=>'0');
signal twopt5 :sfixed(19 downto -12):="00000000000000000010100000000000";
signal zero :sfixed(19 downto -12):="00000000000000000000000000000000";
signal flag : std_logic;
signal c1:sfixed(13 downto -1):="110011001100110";
signal c2:sfixed(15 downto -2);
signal c3:sfixed(1 downto -1):="011";
signal c4:sfixed(7 downto -1):="100000110";
signal c5:sfixed(9 downto -2);

signal outputsh: sfixed(19 downto -12):=(others=>'0');

attribute S : string;
attribute S of c5 : signal is "TRUE";

 

begin

process(clk,pid_input1,pid_error,previousOutput_DispCtrl,previousError_DispCtrl)
begin

if (clk='1' and clk'event) then
--if ((output)>"00000000000000000000000010100000") then
if ((output)>2.5) then
previousOutput_DispCtrl<=previousOutput_DispCtrl-pid_error;
--output1<=twopt5;
outputsh<=twopt5;
--flag<='1';
--elsif (output<"00000000000000000000000000000000") then
elsif (output<0.0) then
previousOutput_DispCtrl<=previousOutput_DispCtrl+pid_error;
--output1<=zero;
outputsh<=zero;
--flag<='0';
else
previousOutput_DispCtrl<=junk;
--output1<=output;
--flag<='0';
outputsh<=output;
end if;

--previousOutput_DispCtrl<=junk;


pid_error <= pid_input0 - pid_input1;


end if;
end process;

output <= (p_gain * pid_error)+ previousOutput_DispCtrl+(i_gain* pid_error)+(d_gain * (previousError_DispCtrl - pid_error)) ;
junk <= resize(output,output2);
pid_input1 <=junk;
--output1<=output;
output1<=outputsh;
outputslv<=to_slv(outputsh);

c5 <= c4*c3;

end Behavioral;

 

With regards

Shalini

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sha@hys
Explorer
Explorer
6,738 Views
Registered: ‎05-31-2015

Hello,

 

       I prefixed each sfixed number with a zero prior to the msb digit so that it is not recognized as negative , also dont make change to number,

 

View solution in original post

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2 Replies
florentw
Moderator
Moderator
4,438 Views
Registered: ‎11-09-2015

Hi sha@hys,

 

I am not familiar with fixed point in VHDL but the "s" in sfixed does not mean signed?

 

In this case you are not doing 196.5 * 1.5 but something like -125 * 1.5. So the result should be negative.

 

So I would expect the first bit to be "1" as in your result. I think this is where you have some confusion.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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sha@hys
Explorer
Explorer
6,739 Views
Registered: ‎05-31-2015

Hello,

 

       I prefixed each sfixed number with a zero prior to the msb digit so that it is not recognized as negative , also dont make change to number,

 

View solution in original post

0 Kudos