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Visitor morlerm
Visitor
8,516 Views
Registered: ‎04-20-2016

generating a faster clock

Hello,

I need to generate a faster clock to drive my ISERDES module in a Spartan-6. I only have a lower speed oscillator connected to the chip, at 25MHz. I would like to drive my ISERDES at 200MHz. I am trying to use a DCM to multiply the input clock by 8 and then use that to drive the ISERDES. However, I am getting routing problems. I am attaching the code below, as well as the error.
Thank you in advance for your help!

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2 Replies
Visitor morlerm
Visitor
8,508 Views
Registered: ‎04-20-2016

Re: generating a faster clock

Thi is my code so far


module mainf( rst,rd_en,din,dout,startsending,valid,wordcount,Pdatai,Ndatai,clkin,wNdatao,wPdatao,count,fastclk,sysclk,wfastclk,dinfifo,div,write);
input rst,rd_en,Pdatai,Ndatai,clkin;
input [7:0] din;
output valid,startsending,wNdatao,wPdatao,fastclk,sysclk,wfastclk,div;
output [11:0]wordcount;
output [7:0] dinfifo;
output [127:0] dout;
output reg [4:0] count;
output write;
assign write=wordcount>=3840? 0 : 1 ;
wire [7:0] dinfifo;

FIFOmem fifo( rst,sysclk,rd_en,dinfifo,dout,write,startsending,valid,wordcount);
iser in
(
// From the system into the device
.DATA_IN_FROM_PINS_P(Pdatai),
.DATA_IN_FROM_PINS_N(Ndatai),
.DATA_IN_TO_DEVICE(dinfifo),

.CLK_IN_P(fastclk), // Differential clock from IOB
.CLK_IN_N(fastclkB),
.CLK_DIV_OUT(div), // Slow clock output
.CLK_RESET(rst),
.IO_RESET(rst)
);

oser out
(
// From the device out to the system
.DATA_OUT_FROM_DEVICE(din),
.DATA_OUT_TO_PINS_P(Pdatao),
.DATA_OUT_TO_PINS_N(Ndatao),

.CLK_IN_P(fastclk), // Differential clock from IOB
.CLK_IN_N(fastclkB),
.CLK_DIV_OUT(divclk), // Slow clock output
.CLK_RESET(c),
.IO_RESET(s)
);
reg S,preS;
assign wPdatao= ((count<5'b00100)|(count>=5'b01100))? 1'bz: Pdatao;
assign wNdatao= ((count<5'b00100)|(count>=5'b01100))? 1'bz: Ndatao;
assign c= (count==5'b01011)? 1'b1 : 1'b0;
assign s= (count==5'b01011)? 1'b1 : 1'b0;
always@(posedge fastclkB )
begin
if(rst)
begin
count=0;
S=0;
preS=0;
end
else
begin
if(count!=5'b01100)
begin
count=count+1;
end
else
begin
preS=S;
S=startsending;
if((S==1)&(preS==0))
count=0;
end
end
end
clks clkSource (
// Clock in ports
.CLK_IN1(clkin), // IN
// Clock out ports
.CLK_OUT1(sysclk), // OUT
.CLK_OUT2(fastclk), // OUT
.CLK_OUT3(fastclkB) ); // OUT

endmodule


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:52:57 04/16/2016
// Design Name:
// Module Name: new
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FIFOmem( rst,sysclk,rd_en,din,dout,write,startsending,valid,wordcount);
input rst,sysclk,rd_en,write;
input [7:0] din;
output [127:0] dout;
output startsending;
output valid;
output reg [11:0] wordcount;
reg [1:0] syscount;
reg [63:0] dout1,dout2;
reg [127:0] regdout;
wire [63:0] doutm;
reg doutCount;
wire write_notFull = write &(~full);
wire [4:0] word_notEmp= (wordcount==0)&(empty==1) ? 1 : wordcount;
assign startsending=!(word_notEmp%5'b10000);
always@(posedge sysclk)
begin
if(rst)
begin
wordcount<=0;
end
else
begin
if(write_notFull)
wordcount<=wordcount+1;
end
end
always@(posedge sysclk)
begin
if(rst)
begin
doutCount=1;
dout1=0;
dout2=0;
end
else
begin
if(valid)
begin
if(doutCount)
begin
dout1=doutm;
end
else
begin
dout2=doutm;
regdout={dout1,dout2};
end
doutCount=doutCount+1;
end
end
end
assign dout=regdout;
fifo FIFO1(
.rst(rst),
.rd_clk(sysclk),
.wr_clk(sysclk),
.din(din), // Bus [7 : 0]
.wr_en(write_notFull),
.rd_en(rd_en),
.dout(doutm), // Bus [63 : 0]
.full(full),
.empty(empty),
.valid(valid)
);

endmodule




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Teacher muzaffer
Teacher
8,345 Views
Registered: ‎03-31-2012

Re: generating a faster clock

You don't show the error so we don't have enough information for a meaningful answer.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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