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Visitor abysslover
Visitor
13,203 Views
Registered: ‎07-22-2011

generating multiple clocking source with SP605

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I'm a newbie to FPGA field. Although I took a course on VLSI theory last semester, it have done with little practical approaches.

I have to design a prototype board until August. It is so heavy load but there is no one else capable of reading verilog code.. My major is computer science and RF engineering.

 

My concern is generating two clocking signals from the port done with SMA soldering such as J32 TXP and J33 TXN.

 

Yesterday, my first board, Spartan 6 SP 605, was arrived. My mission is to interface with ADC and DAC evaluation board from TI.

At a glance, my first challenge should be generating clocking signal from FPGA.

 

 I spend all night to find the information. I've read ug382. It was understandable but I do not know how to realize it with Verilog. Next thing I found was Clocking Wizard. I did not change the configuration:

Input Clock : primary

Input Freq(MHz) : 100.000

Input Jitter(UI) : 0.010

Output Clock : CLK_OUT1

Output Freq(MHz) : 100.000

Phase(degrees) : 0.000

Duty Cycle(%) : 50.0

Pk-to-Pk Jitter(ps) : 200.000

Phase Error(ps) : 50.000

 

It seemed to generate some hidden codes. Following the user manual or related documentations, I made a testbench for core. It works in ISim as I expected. The next step was writing a module.

 

module ClockFirst_md(CLK_IN1, RESET, CLK_OUT1, LOCKED);
 // Inputs
 input CLK_IN1;
 input RESET;

 // Outputs
 output CLK_OUT1;
 output LOCKED;

 // Instantiate the Unit Under Test (UUT)
 ClockFirst uut (
  .CLK_IN1(CLK_IN1),
  .CLK_OUT1(CLK_OUT1),
  .RESET(RESET),
  .LOCKED(LOCKED)
 );


endmodule

 

There was only one warning :

Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=1,CLKFX_MULTIPLY=4,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=10.0,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="1X",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "\work\lab\ClockGenerator\ipcore_dir/ClockFirst.v" Line 128: Assignment to status_int ignored, since the identifier is never used

 

This warning is not important. I supposed the Synthesize is successful.

 

Then, I clicked Implement Design button. the Translate had no problem but the Map process has some problems.

 

ERROR:Place:1206 - This design contains a global buffer instance,
   <uut/clkout1_buf>, driving the net, <CLK_OUT1_OBUF>, that is driving the
   following (first 30) non-clock source pins off chip.
   < PIN: CLK_OUT1.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
ERROR:Place:1136 - This design contains a global buffer instance,
   <uut/clkout1_buf>, driving the net, <CLK_OUT1_OBUF>, that is driving the
   following (first 30) non-clock source pins.
   < PIN: CLK_OUT1.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "uut/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

I found a solution about this problem in this forum. Then I stucked in this source code..

 

module ClockFirst_md(CLK_IN1, RESET, CLK_OUT1, LOCKED, CE);
 // Inputs
 input CLK_IN1;
 input RESET;
 input CE;

 // Outputs
 wire CLK_IOUT;
 output CLK_OUT1;
 output LOCKED;

 // Instantiate the Unit Under Test (UUT)
 ClockFirst uut (
  .CLK_IN1(CLK_IN1),
  .CLK_OUT1(CLK_IOUT),
  .RESET(RESET),
  .LOCKED(LOCKED)
 );
 
 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q 
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
                   //   set/reset
) ODDR2_inst (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IN1), // 1-bit clock input from PLL
   .C1(~CLK_IN1), // 1-bit inverted clock input from PLL
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);


endmodule

 

Current error is :

ERROR:Xst:2035 - Port <CLK_IN1> has illegal connections. This port is connected to an input buffer and other components.


What I'm trying to do is generate two clocking signal. If this code fixed correctly, I will be able to connect one signal to ADC evaluation board as a reference clock and another one to ADC board as an analog signal to be sampled and processed again in the SP605.

 

In addition, my major is not directly VLSI related, however, I have to design this board in support of modulator and demodulator IC implementation. Sharing some expertise or knowledge is appreciated. Thank you for reading.

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1 Solution

Accepted Solutions
Teacher eteam00
Teacher
12,268 Views
Registered: ‎07-21-2009

Re: SP605 and generate multiple clock

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This is getting a bit old.  Suggested code:

 

module ClockSecond (
 // Inputs
input SYSCLK_P, SYSCLK_N,  // 200MHz differential input clock
 
// Outputs
output wire CLK_OUT200_P, CLK_OUT200_N,  // 200MHz output clock, diff pair
output wire CLK_OUT100_P, CLK_OUT100_N  // 100MHz output clock, diff pair
);

IBUFGDS  IBUFGDS_inst (
      .O(CLOCK200),  // 200MHz global clock
      .I(SYSCLK_P),  // Diff_p clock bfr input (connect directly to top-level port)
      .IB(SYSCLK_N) // Diff_n clock bfr input (connect directly to top-level port)
   );

 

(* IOB="TRUE" *)  reg  CLK_BFR100;

reg  CLK_BFR100_copy;
wire CLK_BFR200;

ODDR2 #(
    .DDR_ALIGNMENT("NONE")) // Sets output alignment to "NONE", "C0" or "C1"
    ODDR2_CLK200 (
   .Q(CLK_BFR200),   // 200MHz square wave
   .C0(CLOCK200), // 200MHz input clock
   .C1(~CLOCK200), // 200MHz input clock, use falling edge
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input, always de-asserted
   .S(1'b0)    // 1-bit set input, always de-asserted
 );

OBUFDS OBUFDS_CLK200 (
      .O(CLK_OUT200_P),    // Diff_p output (connect directly to top-level port)
      .OB(CLK_OUT200_N),   // Diff_n output (connect directly to top-level port)
      .I(CLK_BFR200)       // Buffer input
   );

always @(posedge CLOCK200) begin

           CLK_BFR100_copy <= ~CLK_BFR100_copy// divide by 2, 100MHz

  CLK_BFR100 <= CLK_BFR100_copy// shadow register placed in IOB, 100MHz output

  end

OBUFDS OBUFDS_CLK100 (
      .O(CLK_OUT100_P),    // Diff_p output (connect directly to top-level port)
      .OB(CLK_OUT100_N),   // Diff_n output (connect directly to top-level port)
      .I(CLK_BFR100)       // Buffer input
   );
endmodule

 

Notice the changes:

  • PLL is not needed.  Just use the 200MHz sysclk (differential) input, with appropriate buffering.
  • 100MHz output clock is generated from 200MHz global clock.
  • Demonstrates true differential output (with or without ODDR2 blocks) done properly.

-- Bob Elkind

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Summary:
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36 Replies
Teacher eteam00
Teacher
13,189 Views
Registered: ‎07-21-2009

Re: SP605 and generate multiple clock

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An input pin (signal) is buffered.  You may not use the input pin signal anywhere else but the buffer input.

 

PAD           IBUF buffer

+--+   IN_SIG     |\   BFR_SIG

|  |------+------>| >-------------> (legal connections)

+--+      |       |/

          |  

          +----> (illegal connections!)

 

Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor abysslover
Visitor
13,182 Views
Registered: ‎07-22-2011

Re: SP605 and generate multiple clock

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Honestly, I do not familar with the digital hardware but have to be familiarized from now on.

My background is quite far from this domain. I'm familiar with software code or RF terms..

 

If you don't mind, could you explain your explanation more in detail?

I have never done this type of project.

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Teacher eteam00
Teacher
13,161 Views
Registered: ‎07-21-2009

Re: SP605 and generate multiple clock

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The signal connecting the input pad and the input buffer may not connect directly to anything else.  This is a limit of the Spartan-6 IO block and interconnect.  I have modified your source code as follows, with changes marked in RED:

 

module ClockFirst_md(CLK_IN_PAD, RESET, CLK_OUT1, LOCKED, CE);
    // Inputs
    input CLK_IN_PAD;
    input RESET;
    input CE;

    // Outputs
    wire CLK_IOUT;
    output CLK_OUT1;
    output LOCKED;
    wire CLK_IN1;

   BUFG BUFG_CLKIN (
      .O(CLK_IN1), // 1-bit output Clock buffer output
      .I(CLK_IN_PAD)  // 1-bit input Clock buffer input
   );

    // Instantiate the Unit Under Test (UUT)
    ClockFirst uut (
        .CLK_IN1(CLK_IN1),
        .CLK_OUT1(CLK_IOUT),
        .RESET(RESET),
        .LOCKED(LOCKED)
    );
   
    ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q 
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
                   //   set/reset
) ODDR2_inst (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IN1), // 1-bit clock input from PLL
   .C1(~CLK_IN1), // 1-bit inverted clock input from PLL
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);
endmodule

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Instructor
Instructor
13,152 Views
Registered: ‎08-14-2007

Re: SP605 and generate multiple clock

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You should also change the port name for CLK_IN1 to CLK_IN_PAD:

 

module ClockFirst_md(CLK_IN_PAD, RESET, CLK_OUT1, LOCKED, CE);
    // Inputs
    input CLK_IN_PAD;

By the way, this is one reason to use the Verilog 2001 port syntax which avoids duplicate

port name entry:

 

module ClockFirst_md

(

    input CLK_IN_PAD,

    input RESET,

    output CLK_OUT1,

    output LOCKED,

    input CE

);
    wire CLK_IN1;

 . . .

 

Regards,

Gabor

-- Gabor
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Teacher eteam00
Teacher
13,147 Views
Registered: ‎07-21-2009

Re: SP605 and generate multiple clock

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Thanks, Gabor.  I updated my post.

 

-- Bob

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor abysslover
Visitor
13,142 Views
Registered: ‎07-22-2011

Re: SP605 and generate multiple clock

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Thanks, eteam00 and Gabor.

I applied this code into my original one. I'm reading again UG323 to understand what I do.

 

IBUF buffer

|\   BFR_SIG

| >

|/

 

I think that IBUF is realized as follow:

 

// Initiate a Global Clock Buffer <- I added as I understood.

BUFG BUFG_CLKIN (
  .O(CLK_IN1),  // 1-bit output Clock buffer output
  .I(CLK_IN_PAD) // 1-bit input Clock buffer input
 );

 

CLK_IN_PAD(input) and CLK_IN1(wire) are connected through a global clock buffer. If it is true, it will be really interesting to see the trasition from the code to a digitally working function block. Now, the signal flows through CLK_IN_PAD -> CLK_IN1 -> CLK_IN1 of ClockFirst Core(Clocking Wizard) ->CLK_IOUT.

In the initial code, the parameters are CLK_IN1, RESET, CLK_OUT1, LOCKED, CE. Therefore, there was no output. I changed the code again.

 

module ClockFirst_md(CLK_IN_PAD, RESET, CLK_IOUT, LOCKED, CE);
 // Inputs
 input CLK_IN_PAD;
 input RESET;
 input CE;

 // Outputs
 output CLK_IOUT;
// output CLK_OUT1;
 output LOCKED;
 wire CLK_IN1;
 
 // Initiate a Global Clock Buffer
 BUFG BUFG_CLKIN (
  .O(CLK_IN1),  // 1-bit output Clock buffer output
  .I(CLK_IN_PAD) // 1-bit input Clock buffer input
 );

 // Instantiate the Unit Under Test (UUT)
 ClockFirst uut (
  .CLK_IN1(CLK_IN1),
  .CLK_OUT1(CLK_IOUT),
  .RESET(RESET),
  .LOCKED(LOCKED)
 );

 

 
 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q 
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
                   //   set/reset
) ODDR2_inst (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IN1), // 1-bit clock input from PLL
   .C1(~CLK_IN1), // 1-bit inverted clock input from PLL
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);


endmodule

 

Then, I got this error:

ERROR:NgdBuild:770 - IBUFG 'uut/clkin1_buf' and BUFG 'BUFG_CLKIN' on net
   'CLK_IN1' are lined up in series. Buffers of the same direction cannot be
   placed in series.
ERROR:NgdBuild:462 - input pad net 'CLK_IN1' drives multiple buffers:
ERROR:NgdBuild:924 - input pad net 'CLK_IN1' is driving non-buffer primitives:

 

It indicates, if I'm right, ClockFirst instance uut has an internal buffer, clkin1_buf.

 

I found this question.

http://forums.xilinx.com/t5/Archived-ISE-issues/Error-message-Buffers-of-the-same-direction-cannot-be-placed-in/td-p/9731

 

I clicked Manage Cores to check the resource estimation. They are 1 DCM_CLKGEN, 1 IBUFG, 1BUFG.

jimwu seems to point out correctly what I did(, but I'm not sure.). He suggested that nipbor should go back to CoreGen and regenerate the DCM files with "Internal" for "CLKIN" Source.

 

In Clocking Wizard, there is the Input Clock Information. I can change the Source type. Those are :

Single ended clock capable pin, Differential clock capable pin, Single ended non clock pin, Differential non clock pin, Global buffer, No buffer.

 

What is the Internal for CLKIN Source among them?

 

Regards,

Euncheon

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Scholar joelby
Scholar
13,124 Views
Registered: ‎10-05-2010

Re: SP605 and generate multiple clock

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Try "No buffer" in place of "Internal". Perhaps the option has been renamed at some point.

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Teacher eteam00
Teacher
13,122 Views
Registered: ‎07-21-2009

Re: SP605 and generate multiple clock

Jump to solution

jimwu seems to point out correctly what I did(, but I'm not sure.). He suggested that nipbor should go back to CoreGen and regenerate the DCM files with "Internal" for "CLKIN" Source.

 

Jimwu's advice is good, and applies for your design as well.

 

In Clocking Wizard, there is the Input Clock Information. I can change the Source type. Those are :

Single ended clock capable pin, Differential clock capable pin, Single ended non clock pin, Differential non clock pin, Global buffer, No buffer.

 

What is the "Internal for CLKIN Source" among them?

 

Good question.

 

Jim Wu's advice is to tell the Clock Gen wizard that the input clock (input to the generated clockgen 'core') is already buffered.  This is what Jim meant by 'internal'.  In Clock Gen terms, this corresponds to 'no buffer'.

 

I could be wrong on this, but it will take you but a few minutes, at most, to check this.  As you have already learned, checking the resource estimation gives you a clue what the Clock Gen wizard is doing.  From what you've shown us, there should be just a single BUFG in the Clock Gen resource list -- for the PLL/DCM output clock.

 

Do you understand the original problem in your design, and what the error message was trying to tell you?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor abysslover
Visitor
13,118 Views
Registered: ‎07-22-2011

Re: SP605 and generate multiple clock

Jump to solution

Thanks, Joel and eteam00.

 

I tried all options before you replied and it seems working but I do not have confidence of the result. With "No buffer" option, I changed the code as follow:

 

module ClockFirst_md(CLK_IN_PAD, RESET, CLK_OUT1, LOCKED, CE);
 // Inputs
 input CLK_IN_PAD;
 input RESET;
 input CE;

 

 // Outputs
 wire CLK_IOUT;
 output CLK_OUT1;
 output LOCKED;
 wire CLK_IN1;
 
 // Initiate a Global Clock Buffer
 BUFG BUFG_CLKIN (
  .O(CLK_IN1),  // 1-bit output Clock buffer output
  .I(CLK_IN_PAD) // 1-bit input Clock buffer input
 );

 

 // Instantiate the Unit Under Test (UUT)
 ClockFirst uut (
  .CLK_IN1(CLK_IN1),
  .CLK_OUT1(CLK_IOUT),
  .RESET(RESET),
  .LOCKED(LOCKED)
 );
 
 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment 
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q  
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
                   //   set/reset
) ODDR2_inst (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IN1), // 1-bit clock input from PLL
   .C1(~CLK_IN1), // 1-bit inverted clock input from PLL
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

 

endmodule

 

The Gernerate Programming File was successful. When taking a look at the code, however, there is no relevant with the output port, CLK_OUT1.

 

The signal flows are as follow :

  1. CLK_IN_PAD -> BUFG_CLKIN(of BUFG) -> CLK_IN1 -> uut(of ClockFirst) -> CLK_IOUT
  2. CLK_OUT1, CLK_IN1, ~CLK_IN1 -> ODDR2_inst(of ODDR2)

I made a testbench for FirstClock core. The ISim worked correctly. I do not know how to route signal from CLK_IOUT to external physical SMA port.

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Scholar joelby
Scholar
8,636 Views
Registered: ‎10-05-2010

Re: SP605 and generate multiple clock

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When taking a look at the code, however, there is no relevant with the output port, CLK_OUT1.


Sorry, what do you mean by this?

 


I made a testbench for FirstClock core. The ISim worked correctly. I do not know how to route signal from CLK_IOUT to external physical SMA port.


You need to use a UCF file to map between your top level module's ports and the FPGA's actual, physical pins.

 

An example UCF file for the SP605 can be found at the SP605 documentation page. The GPIO SMA connectors are A3 (USER_SMA_GPIO_N) and B3 (USER_SMA_GPIO_P) so you choose either of these with:

 

NET "CLK_OUT1" LOC = "A3";
# or
NET "CLK_OUT1" LOC = "B3";

 You'll need to define ports for CLK_IN_PAD, RESET, LOCKED and CE too - possibly an oscillator, an SPST pushbutton, an LED, and a DIP switch respectively, or whatever else takes your fancy.

 

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Scholar joelby
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Re: SP605 and generate multiple clock

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Sorry, now I see what you mean.

 

Try this:

 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment 
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q  
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
                   //   set/reset
) ODDR2_inst (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IOUT), // 1-bit clock input from PLL
   .C1(~CLK_IOUT), // 1-bit inverted clock input from PLL
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

 

Otherwise you'll be outputting the system clock (CLK_IN1), rather than the output of ClockFirst.

 

 

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Teacher eteam00
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Re: SP605 and generate multiple clock

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@joelby wrote:

Sorry, now I see what you mean.

 

Try this:

 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment 
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q  
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
                   //   set/reset
) ODDR2_inst (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IOUT), // 1-bit clock input from PLL
   .C1(~CLK_IOUT), // 1-bit inverted clock input from PLL
   .CE(CE), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);


This change by Joelby is the only change needed to make the original code (in post #1) work correctly without errors.  The other changes with BUFGs would not be necessary.  At least you learned a bit about Spartan-6 clock distribution and buffering along the way.

 

-- Bob Elkind

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Visitor abysslover
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Re: SP605 and generate multiple clock

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I really appreciate your patience toward the final result, eteam00 and joelby.

I was not able to see the result first time in a test bench since I forgot changing the value of CE to 1.

With the statement "CE=1", the testbench shows the output clock of FirstClock.

 

module ClockFirst_md_tb;

 // Inputs
 reg CLK_IN_PAD;
 reg RESET;
 reg CE;

 // Outputs
 wire CLK_OUT1;
 wire LOCKED;

 

 // Instantiate the Unit Under Test (UUT)
 ClockFirst_md uut (
  .CLK_IN_PAD(CLK_IN_PAD),
  .RESET(RESET),
  .CLK_OUT1(CLK_OUT1),
  .LOCKED(LOCKED),
  .CE(CE)
 );

 

 initial begin
  // Initialize Inputs
  CLK_IN_PAD = 0;
  RESET = 1;
  CE = 0;

  // Wait 100 ns for global reset to finish
  #100;
  RESET = 0;
  CE = 1;
 end
 always begin
  #10 CLK_IN_PAD = ~CLK_IN_PAD;
 end
endmodule

 

After joelby replied the UCF, I've been reading about UCF. Is UCF working as pin mapping?

 

I added a new source with the type, "Implementation Constraints File".

Then, typed as:

NET "CLK_OUT1" LOC = "A3";

In the Master UCF, location "A3" refers to "USER_SMA_GPIO_N".

 

I'm currently watching ISE iMPACT GUI. I do not know about this tool. I have to search for tutorial of this tool.

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Teacher eteam00
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Re: SP605 and generate multiple clock

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Is UCF working as pin mapping?

 

Yes.  It also contains timing constraints.

 

After the changes which you have made, does your design compile without error messages?

 

-- Bob Elkind

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Visitor abysslover
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Re: SP605 and generate multiple clock

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There are some warnings but Generating Programming file was successful. I do not know potential problems. Based upon ISim, I have to add a constraint for CE port. Quite honestly, I cannot stand anymore due to the sleep deprivation. I'm going to visit the forum tomorrow.

Thanks Bob.

 

Regards,

Lim, Euncheon

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Scholar joelby
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Re: SP605 and generate multiple clock

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Unless you really do want to control the clock output from an external pin, you could just replace CE with a '1':

 

) ODDR2_inst (

   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_IOUT), // 1-bit clock input from PLL
   .C1(~CLK_IOUT), // 1-bit inverted clock input from PLL
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input

 

If you haven't given NET constraints for CLK_IN_PAD, RESET, LOCKED, and CE, you'll either get an error or they'll be assigned to pins arbitrarily and your desisgn won't work. The tools can't know what's connected on your development board and what you might want to do with your signals.

 

Here are some suggestions:

 

NET "CLK_IN_PAD" LOC="AB13"; ## 27 MHz clock
NET "RESET" LOC="F3"; ## SW4 pushbutton
NET "LOCKED" LOC="D17"; ## GPIO LED 0
NET "CE" LOC="C18"; ## SW2 DIP switch 1

 

In your first post you mentioned that you'd told the wizard that your clock input was 100 MHz, but the SP605 only has a 200 MHz oscillator and (by default) a 27 MHz oscillator. The 200 MHz oscillator actually has differential outputs, so if you want to use this one, you'll need to add another top level port for the second clock pad and then either tell the wizard to use the "differential clock capable pin"  or manually instantiate an IBUFGDS.


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Visitor abysslover
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Re: SP605 and generate multiple clock

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joelby, you're right. My first problem has not solved yet. I marked eteam00's first answer as the solution since I want to express my appreciation to him.

 

I only focused on the concept rather than a practical approach. Actually, I have to utilize 200-MHz oscillator instead of 27-MHz one to interface with a high-speed ADC, DAC evaluation board from Texas Instrument.

 

I've tried with this configuration in Clocking Wizard:

Clocking Features : default

Clock Manager Type : default

Input Clock

  • Input Freq (MHz) : 200.000
  • Source : Differential clock capable pin, others : default

Output Clock Settings

  • CLK_OUT1 : Output Freq(MHz) Requested : 100.000, others : default
  • CLK_OUT2 : Output Freq(MHz) Requested : 200.000, others : default

The core name is dualClockSource and this is the code for ClockSecond verilog module:

 

module ClockSecond(CLK_IN1_P, CLK_IN1_N, RESET, CLK_OUT1, CLK_OUT2, LOCKED);
 // Inputs
 input CLK_IN1_P;
 input CLK_IN1_N;
 input RESET;
 
 // Outputs
 output CLK_OUT1;
 output CLK_OUT2;
 output LOCKED;
 wire CLK_OUT1_connector;
 wire CLK_OUT2_connector;

 

 // Instantiate the clocking source
 ClockFor200MHz dualClockSource (
  .CLK_IN1_P(CLK_IN1_P),
  .CLK_IN1_N(CLK_IN1_N),
  .CLK_OUT1(CLK_OUT1_connector),
  .CLK_OUT2(CLK_OUT2_connector),
  .RESET(RESET),
  .LOCKED(LOCKED)
 );
 
 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q 
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC"
                   //   set/reset
) ODDR2ForCLK_OUT1 (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_OUT1_connector), // 1-bit clock input from PLL
   .C1(~CLK_OUT1_connector), // 1-bit inverted clock input from PLL
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment 
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q  
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
                   //   set/reset
) ODDR2ForCLK_OUT2 (
   .Q(CLK_OUT2),   // 1-bit DDR output data
   .C0(CLK_OUT2_connector), // 1-bit clock input from PLL
   .C1(~CLK_OUT2_connector), // 1-bit inverted clock input from PLL
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);
endmodule

 

Generate Programming File was successful but I have not tried to simulate this module in a testbench code.

Regards,

Euncheon

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Scholar joelby
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Re: SP605 and generate multiple clock

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joelby, you're right. My first problem has not solved yet. I marked eteam00's first answer as the solution since I want to express my appreciation to him.


I'm sure Bob appreciates it, even though he's already got a garage full of Xilinx kudos prizes.

 

If you want to use the 200 MHz oscillator (which will be much better for driving your ADC), you should use the "differential clock capable pin" and add a new input to your module called CLK_IN_PAD_N, which will be the other side of your 200 MHz oscillator. Then add an appropriate constraint for this pin (and change CLK_IN_PAD to the positive end of the 200 MHz oscillator). This will add another input port to ClockFirst, so examine its new HDL instantiation template and update your code.


While configuring a Clocking-Wizard-core instance, I specified the input source as "No Buffer".

What can I use other options such as "Differential clock capable pin"?


Are you asking what the other options are for?

 

  • Single ended clock capable pin - generates an IBUFG, connects directly to GCLK (clock) pad
  • Differential clock capable pin - generates an IBUFGDS, connects directly to differential pair of GCLK pads
  • Single ended non clock pin - similar to above, but works with non-GCLK pads
  • Differential non clock pin - similar to above, but works with non-GCLK pads
  • Global buffer - generates an BUFG. You need to connect it to a pad or the output of an IBUFDS
  • No buffer - doesn't generate anything. You need to connect it to the output of a BUFG.

I haven't checked to see what the non-clock pin options actually generate (presumably a BUFG and a nasty warning) but these should be avoided if possible.

 

Teacher eteam00
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Re: SP605 and generate multiple clock

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joelby, you're right. My first problem has not solved yet. I marked eteam00's first answer as the solution since I want to express my appreciation to him.

 

I appreciate the gesture.  Not to be ungrateful, but I prefer a cold beer!  (just kidding, and I hope there are no underage kids reading this forum).

 

You are able to 'unmark' my post as the solution.  If you do so, I won't be insulted in the least bit.  Joelby has given you good answers and guidance.

 

-- Bob Elkind

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Visitor abysslover
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Re: SP605 and generate multiple clock

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While editing the last question, both of you replied to my post. The only thing I was able to do is giving Kudos.

 

I removed BUFG instance, which is unnecessary according to the error message.

I added two wires for the outputs from a ClockFor200MHz core, which is newly generated.

The wired signal should be outputted so that I initiated two ODDR2 instances for the each output.

Is my logic correct or is there any correction needed?

 

Regards,

Euncheon

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Scholar joelby
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Re: SP605 and generate multiple clock

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That looks about right (though I found the _connector suffix a bit confusing - I usually think about this being a physical connector rather than an internal signal). Does it all work now? :)

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Teacher eteam00
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Re: SP605 and generate multiple clock

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Important things first:

 

I'm sure Bob appreciates it, even though he's already got a garage full of Xilinx kudos prizes.

 

In case you're wondering, I've received a Xilinx kudos prize -- one.  It represents a token of thanks and appreciation for the time and thought spent helping out in the forums, nothing more.  As a thoughtful gesture from Xilinx, I appreciate the acknowledgment.  There is still quite a bit of room left in my garage, so at the rate at which my forum activity is able to fill the garage....  I may have to stick with my day job, for now.

 

Keep up the good work, Joel.

 

The wired signal should be outputted so that I initiated two ODDR2 instances for the each output.

Is my logic correct or is there any correction needed?

You have made a set of fascinating and thought-provoking mistakes, easily worthy of forum discussion.

 

First:  clocks (as in PLL outputs) can be 're-used'.  I'm guessing that the two ODDR blocks are supposed to generate a differential output clock pair.  There is no need to generate a unique output clock for each ODDR primitive.  If the two ODDR blocks are clocked at different frequencies, then perhaps the PLL outputs are not duplicates, after all.

 

Second:  For differential output, use OBUFDS.  Absent source code comments to the contrary, it appears that duplicate ODDR blocks are used to generate what *should* be differential outputs of a single clock.  If this is the case, then a single ODDR block is sufficient, followed by an OBUFDS output buffer (output buffer with differential outputs).  The package pins to which  the differential outputs are assigned should must be a true differential pair.

 

Third:  ODDR "differential" polarity fail.  It may well be that the duplicate ODDR blocks are unnecessary, only a single ODDR block is needed for differential output.  Notwithstanding, if you were interested in generating two complementary outputs from two ODDR blocks, the correct implementation is:

 

  • Connect a single clock to both ODDRs, identically.  This ensures better matched timing, short of true differential output.
  • If one ODDR has D0 and D1 inputs tied to '0' and '1', respectively, the other ODDR should have D0 and D1 tied to '1' and '0', respectively.  This would achieve the desired opposite output polarity from the two blocks.

These are all beginner's mistakes, and make for excellent 'teaching moments'.  The more mistakes like these which you can get out of the way sooner rather than later, the quicker you can move on to 'experienced designer' mistakes, like the rest of us!  You learn much more from making (and fixing) mistakes than by not making mistakes at all.

 

-- Bob Elkind

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Visitor abysslover
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Re: SP605 and generate multiple clock

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I'm curious how the UCF works.

After changing the code, I've been looking for appropriate NET statement in order to set positive and negative input clock.

I commented out this statement in the UCF:

 #"CLK_IN_PAD" LOC="AB13"; ## 27 MHz clock

 

I did not specify the 200-MHz input clock in the UCF but there is no error found through Map, Place & Route and Generate-Programming-File process.

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Scholar joelby
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Re: SP605 and generate multiple clock

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;)

CLK_OUT1 and CLK_OUT2 are different frequencies (100, 200 MHz) according to post 18, so the dual ODDR approach should be correct. Euncheon, do you need to clock your ADC differentially or with a single ended clock?

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Scholar joelby
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Re: SP605 and generate multiple clock

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@abysslover wrote:

I'm curious how the UCF works.

After changing the code, I've been looking for appropriate NET statement in order to set positive and negative input clock.

I commented out this statement in the UCF:

 #"CLK_IN_PAD" LOC="AB13"; ## 27 MHz clock

 

I did not specify the 200-MHz input clock in the UCF but there is no error found through Map, Place & Route and Generate-Programming-File process.


I recall that if you don't constrain the nets, the tools pick random pins for the implementation, which is pretty much never what you want it to do (I think I usually get an error when I try this by accident, though).

 

Make sure you always use the correct net constraints. Have a look in the appendices of the SP605 Hardware User Guide to see where all of your peripherals are connected.

 

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Teacher eteam00
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Re: SP605 and generate multiple clock

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CLK_OUT1 and CLK_OUT2 are different frequencies (100, 200 MHz) according to post 18, so the dual ODDR approach should be correct.

 

Ahhh, thank you.  I missed that.  In which case, the logical question is:

While clocking the 200MHz ODDR with a 200MHz clock, why not use the same 200MHz clock to generate the 100MHz clock output, with an SDR register configured as a divide-by-two (e.g.  D <= ~Q)?

 

The dual-clock, dual ODDR implementation will burn more power, and may be more difficult to place and route.

 

-- Bob Elkind

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Re: SP605 and generate multiple clock

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Automatic definition on each NET statment is not my intention. I have to read ug526 first to specify them correctly. I have four output clocks. CLK_OUT1(100MHz, 0 degree), CLK_OUT2(100MHz, 180 degree), CLK_OUT3(200MHz, 0 degree), CLK_OUT4(200MHz, 180 degree). This is the current source code:

module ClockSecond(CLK_IN1_P, CLK_IN1_N, RESET, CLK_OUT1, CLK_OUT2, LOCKED);
 // Inputs
 input CLK_IN1_P;
 input CLK_IN1_N;
 input RESET;
 
 // Outputs
 output CLK_OUT1;
 output CLK_OUT2;
 output LOCKED;
 wire CLK_OUT1_wire;
 wire inverted_CLK_OUT1_wire;
 wire CLK_OUT2_wire;
 wire inverted_CLK_OUT2_wire;

 // Instantiate the clocking source
 ClockFor200MHz dualClockSource (
  .CLK_IN1_P(CLK_IN1_P),
  .CLK_IN1_N(CLK_IN1_N),
  .CLK_OUT1(CLK_OUT1_wire),
  .CLK_OUT2(inverted_CLK_OUT1_wire),
  .CLK_OUT3(CLK_OUT2_wire),
  .CLK_OUT4(inverted_CLK_OUT2_wire),
  .RESET(RESET),
  .LOCKED(LOCKED)
 );
 
 ODDR2 #(
   // The following parameters specify the behavior of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
   ) ODDR2ForCLK_OUT1 (
   .Q(CLK_OUT1),   // 1-bit DDR output data
   .C0(CLK_OUT1_wire), // 1-bit clock input from PLL
   .C1(inverted_CLK_OUT1_wire), // 1-bit inverted clock input from PLL
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
 );

 ODDR2 #(
   // The following parameters specify the behavior of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
   ) ODDR2ForCLK_OUT2 (
   .Q(CLK_OUT2),   // 1-bit DDR output data
   .C0(CLK_OUT2_wire), // 1-bit clock input from PLL
   .C1(inverted_CLK_OUT2_wire), // 1-bit inverted clock input from PLL
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);
endmodule

 

I found the 200-MHz clock pair and changed the UCF as follow:

NET "CLK_IN1_P" LOC = "K21";   ## positive system clock at 200 MHz
NET "CLK_IN1_N" LOC = "K22";   ## negative system clock at 200 MHz
NET "CLK_OUT1" LOC = "B3"; ## USER_SMA_GPIO_P
NET "CLK_OUT2" LOC = "A3"; ## USER_SMA_GPIO_N
NET "RESET" LOC = "F3";    ## 2   on SW4 pushbutton (active-high)
NET "LOCKED" LOC="D17";  ## GPIO LED 0

 

Then, I got an error again:

ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not placed at
   a routable clock IOB / BUFIO site pair. The clock IOB component <CLK_IN1_P> is placed at site <PAD107>. The BUFIO
   component <SP6_BUFIO_INSERT_ML_BUFIO2_0> is placed at site <BUFIO2_X3Y11>. Each BUFIO site has a select set of IOBs
   that can drive it. If these IOBs are not used, the connection is not routable You may want to analyze why this
   problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be
   fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list
   of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the
   .ucf file to demote this ERROR to a WARNING.
   < NET "CLK_IN1_P" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

I've found BUFIO2_X3Y11 at page 15 in the ug382 and this answer:

http://www.xilinx.com/support/answers/39184.htm

 

I'm trying to figure it out.

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Scholar joelby
Scholar
8,409 Views
Registered: ‎10-05-2010

Re: SP605 and generate multiple clock

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From what I recall, the forum consensus seems to be that you don't need to use the clocking wizard to generate 0 and 180 degree clocks - just use:

 

.C0(CLK_OUT1_wire),
.C1(~CLK_OUT1_wire),

As you were previously. Does it all work properly when you do it that way?

 

Does your ADC require a single ended or differential clock signal?

 

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Visitor abysslover
Visitor
8,406 Views
Registered: ‎07-22-2011

Re: SP605 and generate multiple clock

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After you asked about the type of clock, I've read the datasheet of the evaluation board(ADA4226EVM). The original test setup connection is as follow:

    1. Connect ADS4226EVM to TSW1200 EVM
    2. Connect 5V power to banana jack at J10; connect ground to J12
    3. Connect USB cable to programming computer at J17
    4. Connect USB and power supply jack to TSW1200
    5. Connect Clock signal through appropriate BPF to J19
    6. Connect input signal through appropriate BPF to J6, J3

 

My purpose is creating a board working as TSW1200 EVM and doing additional signal processing. I have to generate both Clock signal and a sine wave from this FPGA board, if possible. If it is impossible, I should employ a signal generator to generate a sine wave. According to the ADS4226EVM datasheet, the default clock input configuration is 1:4 transformer coupling, and the optional configuration is through clock driver CDC72010.

According to the ADS4226 datasheet, Input clock amplitude differential is Sine wave, ac-coupled is typically 1.5 Vpp, LVPECL, ac-coupled is 1.6 Vpp, LVDS, ac-coupled is 0.7 Vpp, LVCMOS, single-ended, ac-coupled is 1.5 V. However, I'm not making an evaluation board for ADS4226. Therefore, I do not know how much it is important to know the specification of the ADS4226.

 

Is this what you have asked? Honestly, I really do not know which information should I pick up for your question.

 

Regards,

Euncheon

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