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Explorer
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Registered: ‎12-22-2010

is this counter will use dcm or not

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hi 

i have this two  counter that  one of them work  on falling edge of the clock

and second will work in rising edge of clock

i use spartan 3E 

i this system will use dcm to get clock inversion and bulit new gclk net or just put an inverter in input clcok of counter???

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Scholar
Scholar
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Registered: ‎02-27-2008

e,

 

If the device family has an optional inverter on the clock in the CLB, it will infer that.  If the family targeted doesn't have an optional inverter, it may have to pass the clock through a LUT to invert it over general interconnect.  That will generate warnings, to let you know, you are doing something dangerous.



Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
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Registered: ‎02-27-2008

e,

 

Try it both ways, and see how much slack there is in each implmentation.  Both will work, but inverting clocks is messy, and generally not recommended.  Better to create the proper phase clock you desire, and place it on a global clock buffer.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎12-22-2010
DEAR AUSTIN
i mean is the ise optimizer will use dcm to get clock inversion or it will put not gate .
the synthesis result say no dcm use
i am confuse??
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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
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Registered: ‎02-27-2008

The synthesis will not automatically infer a DCM.  That is something you will have to instantiate directly.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎12-22-2010

ohh,I did not know that...

thank you austin

 

this is my code for counter that work on falling edge 

 

counter1:process (clk)
begin
if (clk'event and clk='0'  ) then
counter1<=counter1+1;
end if;
end process;

 

here is this (clk'event and clk='0') will put not gate or this (not(clk)=1)??

 

best regrds 

m.s

 

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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
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Scholar
Scholar
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Registered: ‎02-27-2008

e,

 

If the device family has an optional inverter on the clock in the CLB, it will infer that.  If the family targeted doesn't have an optional inverter, it may have to pass the clock through a LUT to invert it over general interconnect.  That will generate warnings, to let you know, you are doing something dangerous.



Austin Lesea
Principal Engineer
Xilinx San Jose

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Historian
Historian
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Registered: ‎02-25-2008

@eng_man wrote:

hi 

i have this two  counter that  one of them work  on falling edge of the clock

and second will work in rising edge of clock

i use spartan 3E 

i this system will use dcm to get clock inversion and bulit new gclk net or just put an inverter in input clcok of counter???


You are making this way more complicated than necessary.

A DCM is not required.

All Spartan 3E (and pretty much all production Xilinx FPGA device) flip-flops support clocking on either edge.

 

So code it like this:

 

RisingCount : process (clk) is

begin

    if re_enable = '1' then

        re_count <= (re_count + 1) mod ROLLOVER;

    end if;

end process RisingCount;

 

FallingCount : process(clk) is

begin

    if fe_enable = '1' then

        fe_count <= (fe_count + 1) mod ROLLOVER;

    end if;

end process FallingCount;

 

Not hard at all.

----------------------------Yes, I do this for a living.
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Explorer
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Registered: ‎12-22-2010
dear bassman59:
fe_count <= (fe_count + 1) mod ROLLOVER;
can give to us some word about these rows
if fe_enable = '1' then
fe_count <= (fe_count + 1) mod ROLLOVER;
end if;
modules??
fe_enable is this clock or what !??
---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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Historian
Historian
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Registered: ‎02-25-2008

@eng_man wrote:
dear bassman59:
fe_count <= (fe_count + 1) mod ROLLOVER;
can give to us some word about these rows
if fe_enable = '1' then
fe_count <= (fe_count + 1) mod ROLLOVER;
end if;
modules??
fe_enable is this clock or what !??

Please, tell us your FPGA design and VHDL experience. Because this is all pretty much basic stuff.

 

fe_enable is a signal that enables the counter. Where does it come from? I don't know. It's design dependent.

 

The two counter increment lines,

 

    fe_count <= (fe_count + 1) mod ROLLOVER;

 

and its falling-edge compadre

 

    re_count <= (re_count + 1) mod ROLLOVER;

 

simply ensure that the counter rolls over at some defined count value. The constant ROLLOVER should probably be a generic. Note that it does not have to be a power of two (contrary to what some obsolete documentation might say). Also the counter signals re_count and fe_count should probably be defined as naturals with a range 0 to ROLLOVER - 1. NEVER EVER EVER declare a signal which is to be used as a counter as a std_logic_vector. Always use a type which makes sense for counting (natural, integer, signed, unsigned).

 

if the above doesn't make much sense to you then I suggest that you spend quality time with a good VHDL textbook .

----------------------------Yes, I do this for a living.
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Explorer
Explorer
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Registered: ‎12-22-2010
dear bassman59
the word mod confuse me and this what make me tell you explain to us
sorry for that......and thank you
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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Historian
Historian
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Registered: ‎02-25-2008

@eng_man wrote:
dear bassman59
the word mod confuse me and this what make me tell you explain to us
sorry for that......and thank you
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

You can learn all about MOD in any -- and I mean ANY -- VHDL reference.

PLEASE, learn to RTFM.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
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Registered: ‎12-22-2010
okkkkk
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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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