problem when using GTP recovered clock on spartan6-45t

[yetingdd]

Hi,

On Spartan-6 I'm using GTP recovered clock which is TILE0_GTPCLKOUT1_OUT[1].  I'm doing this to  synchrony txpipeclk to trans the SDI 20bits data. These data are also recieved by GTP.

But there is a problem because the TILE0_GTPCLKOUT1_OUT[1] is needed to clean, so there should be a BUFIO2 that followed by a BUFG and a ODDR2, or ISE13.2 will give some errors.

After that, I use the clock from si5324, and tied it to both of  rx PLL and tx PLL to produce txusrclk,txusrclk2 and txpipeclk, and so as the ones of rx. the RX was locked, it meaned HD-SDI video is recieved correctly, but TX was wrong. When I use the WFM 700  of Tektronix, the picture was not good, always shaking.

Does anybody have similar experiences or perhaps a solution to the problem?

some of codes are showed follow

input wire gtpclkout1_1_bufio_in_p,
input wire gtpclkout1_1_bufio_in_n,
output wire gtpclkout1_1_bufio_out,

BUFIO2 #
(
.DIVIDE (1),
.DIVIDE_BYPASS ("TRUE")
)
gtpclkout1_1_dcm2_bufio2_i
(
.I (tile0_gtpclkout1_i[1]),
.DIVCLK (gtpclkout1_1_bufio),
.IOCLK (),
.SERDESSTROBE ()
);

BUFG BUFG_INST(
.I(gtpclkout1_1_bufio),
.O(gtpclkout1_1_bufio2)
);

ODDR2 #(
.DDR_ALIGNMENT ("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT (1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
)
i_ODDR2
(
.C0 (gtpclkout1_1_bufio2), // 1-bit clock input
.C1 (~gtpclkout1_1_bufio2), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D0 (1'b1), // 1-bit data input (associated with C0)
.D1 (1'b0), // 1-bit data input (associated with C1)
.R (1'b0), // 1-bit reset input
.S (1'b0), // 1-bit set input
.Q (gtpclkout1_1_bufio_out) // 1-bit DDR output data
);

IBUFDS #(
.IOSTANDARD ("DEFAULT"),
.DIFF_TERM ("TRUE"))
IBUFDS_i1(
.I (gtpclkout1_1_bufio_in_p),
.IB (gtpclkout1_1_bufio_in_n),
.O (gtpclkout1_1_bufio_in));

// GTP TX interface.
gtp_interface_pll gtp_interface_pll_tx (
.outclk (tile0_txoutclk1_i),
.gtpoutclk (gtpclkout1_1_bufio_in),
.pll_reset_in (gtpclkout1_0_pll_reset),
.data_in (txdata1_20),

.data_out (txdata1_20_gtp),
.usrclk (txusrclk),
.usrclk2 (txusrclk2),
.pipe_clk (txpipeclk),
.pll_locked_out (gtpclkout1_0_pll_locked)
);

// GTP RX interface

gtp_interface_pll gtp_interface_pll_rx(
.outclk (tile0_rxrecclk1_i),
.gtpoutclk (gtpclkout1_1_bufio_in),
.pll_reset_in (gtpclkout1_1_pll_reset),
.data_in (rxdata1_20_gtp),

.data_out (rxdata1_20),
.usrclk (rxusrclk),
.usrclk2 (rxusrclk2),
.pipe_clk (rxpipeclk),
.pll_locked_out (gtpclkout1_1_pll_locked)
);

Thank you.

[yetingdd]

I'm so sorry for My English, it's very poor.  

Can anyone help me? 

[eteam00]

The WFM-700 is a television waveform monitor with SDI/HD-SDI inputs.  It can provide valuable clues for isolating your problem.

Your description of your system is a bit muddled.

What are the inputs to your FPGA, and to what are they connected?

Is your FPGA receiveing HD-SDI, transmitting HD-SDI, or both?

How is the picture content of the HD-SDI output from your FPGA generated?

-- Bob Elkind

[yetingdd]

Hi, eteam00!

     Firstly, I show you my system as picture No. 1.

the codes are showed as following:

    IBUFDS #(
        .IOSTANDARD	("DEFAULT"),
        .DIFF_TERM	("TRUE"))
    ibufds_gtp123_1(
        .I			(PAD_gtp123_1_refclk_p),
        .IB			(PAD_gtp123_1_refclk_n),
        .O			(gtp123_1_refclk));


//
//    BUFIO2 #
//    (
//        .DIVIDE                         (1),
//        .DIVIDE_BYPASS                  ("TRUE")
//    )
//    gtpclkout1_0_txpll_bufio2_i
//    (
//        .I                              (tile0_gtpclkout1_i[0]),
//        .DIVCLK                         (gtpclkout1_0_bufio),
//        .IOCLK                          (),
//        .SERDESSTROBE                   ()
//    );
    
    BUFIO2 #
    (
        .DIVIDE                         (1),
        .DIVIDE_BYPASS                  ("TRUE")
    )
    gtpclkout1_1_dcm2_bufio2_i
    (
        .I                              (tile0_gtpclkout1_i[1]),
        .DIVCLK                         (gtpclkout1_1_bufio),
        .IOCLK                          (),
        .SERDESSTROBE                   ()
    );


    BUFG BUFG_INST(
        .I(gtpclkout1_1_bufio),
        .O(gtpclkout1_1_bufio2)
    );
    
    ODDR2 #(
        .DDR_ALIGNMENT  ("NONE"),         // Sets output alignment to "NONE", "C0" or "C1" 
        .INIT           (1'b0),           // Sets initial state of the Q output to 1'b0 or 1'b1
        .SRTYPE         ("SYNC")          // Specifies "SYNC" or "ASYNC" set/reset
    )
    i_ODDR2
    (     
        .C0   (gtpclkout1_1_bufio2),      // 1-bit clock input
        .C1   (~gtpclkout1_1_bufio2),     // 1-bit clock input
        .CE   (1'b1),                     // 1-bit clock enable input
        .D0   (1'b1),                     // 1-bit data input (associated with C0)
        .D1   (1'b0),                     // 1-bit data input (associated with C1)
        .R    (1'b0),                     // 1-bit reset input
        .S    (1'b0),                     // 1-bit set input
        .Q    (gtpclkout1_1_bufio_out)    // 1-bit DDR output data
    );

    
    IBUFDS #(
        .IOSTANDARD	("DEFAULT"),
        .DIFF_TERM	("TRUE"))
    IBUFDS_i0(
        .I			(CLK_33MHZ_SYSACE_p),
        .IB			(CLK_33MHZ_SYSACE_n),
        .O			(gclk_33M));

    IBUFDS #(
        .IOSTANDARD	("DEFAULT"),
        .DIFF_TERM	("TRUE"))
    IBUFDS_i1(
        .I			(gtpclkout1_1_bufio_in_p),
        .IB			(gtpclkout1_1_bufio_in_n),
        .O			(gtpclkout1_1_bufio_in));

    WIZ1_4_20B#
    (
        .WRAPPER_SIM_GTPRESET_SPEEDUP           (EXAMPLE_SIM_GTPRESET_SPEEDUP),
        .WRAPPER_SIMULATION                     (EXAMPLE_SIMULATION)
    )
    wiz1_4_20b
    (
 
 
 
 
 
 
        //_____________________________________________________________________
        //_____________________________________________________________________
        //TILE0  (X1_Y0)

        //---------------------- Loopback and Powerdown Ports ----------------------
        .TILE0_LOOPBACK0_IN             (3'b000),
        .TILE0_LOOPBACK1_IN             (3'b000),
        //------------------------------- PLL Ports --------------------------------
        .TILE0_CLK00_IN                 (gtp123_1_refclk),
        .TILE0_CLK01_IN                 (gtp123_1_refclk),
        .TILE0_GTPRESET0_IN             (tile0_gtpreset1_i),
        .TILE0_GTPRESET1_IN             (tile0_gtpreset0_i),
        .TILE0_PLLLKDET0_OUT            (tile0_plllkdet1_i),
        .TILE0_PLLLKDET1_OUT            (tile0_plllkdet0_i),
        .TILE0_RESETDONE0_OUT           (tile0_resetdone1_i),
        .TILE0_RESETDONE1_OUT           (tile0_resetdone0_i),
        //----------------- Receive Ports - RX Data Path interface -----------------
        .TILE0_RXDATA0_OUT              (rxdata1_20_gtp),
        .TILE0_RXDATA1_OUT              (tile0_rxdata0_i),
        .TILE0_RXRECCLK0_OUT            (tile0_rxrecclk1_i),
        .TILE0_RXRECCLK1_OUT            (tile0_rxrecclk0_i),
        .TILE0_RXRESET0_IN              (rxreset1),
        .TILE0_RXRESET1_IN              (1'b0),
        .TILE0_RXUSRCLK0_IN             (rxusrclk), 
        .TILE0_RXUSRCLK1_IN             (rxusrclk), 
        .TILE0_RXUSRCLK20_IN            (rxusrclk2),
        .TILE0_RXUSRCLK21_IN            (rxusrclk2),
        //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
        .TILE0_RXCDRRESET0_IN           (tile0_rxcdrreset1_i),
        .TILE0_RXCDRRESET1_IN           (tile0_rxcdrreset0_i),
        .TILE0_RXN0_IN                  (PAD_gtp123_1_rxn),
        .TILE0_RXN1_IN                  (),
        .TILE0_RXP0_IN                  (PAD_gtp123_1_rxp),
        .TILE0_RXP1_IN                  (),
        //--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
        .TILE0_RXBUFRESET0_IN           (tile0_rxbufreset1_i),
        .TILE0_RXBUFRESET1_IN           (tile0_rxbufreset0_i),
        .TILE0_RXBUFSTATUS0_OUT         (tile0_rxbufstatus1_i),
        .TILE0_RXBUFSTATUS1_OUT         (tile0_rxbufstatus0_i),
        //----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
        .TILE0_DADDR_IN                 (gtp101_daddr),
        .TILE0_DCLK_IN                  (gclk_33M),
        .TILE0_DEN_IN                   (gtp101_den),
        .TILE0_DI_IN                    (gtp101_di),
        .TILE0_DRDY_OUT                 (gtp101_drdy),
        .TILE0_DRPDO_OUT                (gtp101_drpo),
        .TILE0_DWE_IN                   (gtp101_dwe),
        //-------------------------- TX/RX Datapath Ports --------------------------
        .TILE0_GTPCLKOUT0_OUT           (tile0_gtpclkout1_i),
        .TILE0_GTPCLKOUT1_OUT           (tile0_gtpclkout0_i),
        //------------- Transmit Ports - TX Buffer and Phase Alignment -------------
        .TILE0_TXBUFSTATUS0_OUT         (tile0_txbufstatus1),
        .TILE0_TXBUFSTATUS1_OUT         (tile0_txbufstatus0),
        //---------------- Transmit Ports - TX Data Path interface -----------------
        .TILE0_TXDATA0_IN               (txdata1_20_gtp),
        .TILE0_TXDATA1_IN               (tile0_txdata0_i),
        .TILE0_TXOUTCLK0_OUT            (tile0_txoutclk1_i),
        .TILE0_TXOUTCLK1_OUT            (tile0_txoutclk0_i),     //  non-clock-specific routing
        .TILE0_TXRESET0_IN              (txreset1),
        .TILE0_TXRESET1_IN              (),
        .TILE0_TXUSRCLK0_IN             (txusrclk),
        .TILE0_TXUSRCLK1_IN             (txusrclk),
        .TILE0_TXUSRCLK20_IN            (txusrclk2),
        .TILE0_TXUSRCLK21_IN            (txusrclk2),
        //------------- Transmit Ports - TX Driver and OOB signalling --------------
        .TILE0_TXN0_OUT                 (PAD_gtp123_1_txn),
        .TILE0_TXN1_OUT                 (),
        .TILE0_TXP0_OUT                 (PAD_gtp123_1_txp),
        .TILE0_TXP1_OUT                 ()
    );
 
assign rx_sd_mode = rx1_mode == 2'b01;   // rx1_mode changes during lock-in 
assign gtpclkout1_0_pll_reset = !tile0_plllkdet1_i; 

// GTP TX interface.
  gtp_interface_pll  gtp_interface_pll_tx (
    .outclk          (),        
    .gtpoutclk       (gtpclkout1_1_bufio_in),      
    .pll_reset_in    (gtpclkout1_0_pll_reset), 
    .data_in         (txdata1_20),        

    .data_out        (txdata1_20_gtp),
    .usrclk          (txusrclk),         
    .usrclk2         (txusrclk2),        
    .pipe_clk        (txpipeclk),       
    .pll_locked_out  (gtpclkout1_0_pll_locked) 
  );
  
// GTP RX interface 

  gtp_interface_pll  gtp_interface_pll_rx(
     .outclk           (),       
     .gtpoutclk        (gtpclkout1_1_bufio_in),     
     .pll_reset_in     (gtpclkout1_1_pll_reset),
     .data_in          (rxdata1_20_gtp),

     .data_out         (rxdata1_20),
     .usrclk           (rxusrclk),         
     .usrclk2          (rxusrclk2),        
     .pipe_clk         (rxpipeclk),       
     .pll_locked_out   (gtpclkout1_1_pll_locked) 
   );

 The signal 'locked' from module 's6_sdi_rx_light_20b' is high, it means SDI RX is correct. But, TX is wrong, the video on the screen of WFM700 is always shaking. And when I switched it to color bar mode, there was nothing on the screen.But when I insteaded 'gtpclkout1_1_buffio_in' by gtpclkout1_0_buffio in GTP TX interface, the color bar was OK.

May be the reference clock 'MGTREFCLK0' should be recovery clock, so I tied again in lab 2.

[yetingdd]

Lab 2.

Because the RX and TX of SDI are located on the same GTP, so the reference should be switched when GTP locked. The new design is showed as following.

When GTP locked, the output of BUFMUX will be recovery clock. (the red lines should be ingored)

Resualt:

'locked' is always changing between logic 1 and logic 0, But the picture on the screen was better than lab 1. There was only some unstable green lines on the picture. And the color bar mode was working well.

       So, why the RX was still unlocked?

NOTE: I has test the PCB with iBert, there was no error.

[yetingdd]

I had tested the system with ibert. But there was nothing wrong with my PCB.