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Visitor desmeto
Visitor
2,346 Views
Registered: ‎07-19-2011

random locks up when running a project

Hello,

 

I'm trying to finish a m68k core on a spartan3E in verilog, actually the system is simulated correctly with isim

But when when running on hardware I got random lock up (I use trace mode of the 68k to debug with real time display

on a vga monitor of internals of the 68k).

 

I'm rather new to fpga but I already recreated an HP86 system in verilog

(see http://sites.google.com/site/olivier2smet2/hpseries80/fpga-hp86b)

 

Actually this bug puzzle me since some months (it's a hobby project)

Does anyone have some hints to track this ?

(clock drift, timing problems ...)

I'm not very good at timing problems (if someone has some good references)

 

Thanks in advance,

 

Olivier

2011-07-19_11-11-19_0.png
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2 Replies
Visitor desmeto
Visitor
2,339 Views
Registered: ‎07-19-2011

Re: random locks up when running a project

Forget the question, I was only making behaviour simulation.

I'm trying to do post-par simulation. It's very tedious as I only have a webpack licence and the simulator is crippling the run-time for a project of this size :(

 

Olivier

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Visitor desmeto
Visitor
2,330 Views
Registered: ‎07-19-2011

Re: random locks up when running a project

Post translate simulation is still ok

Post map simulation is very slow (webpack licence) and goes crazy : many signals stay at Z and are not correctly initialized

Post route can't succeed: first some warnings :

WARNING:NetListWriters:306 - Signal bus Mcount_ram_150us_cy[12 : 0] on block
   MEM_TOP_SOC is not reconstructed, because there are some missing bus signals.

then it takes 5 minutes to simulate 2 ns ... and my bugs appears near 100 ms .... :(

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