01-13-2015 12:54 AM
I connect two Multi Gbit transceiver and do a simulation using Modelsim .One is spartan6 GTP,the other is Virtex4 MGT.
At the beginning ,rxdata of MGT is consistent with the txdata of Spartan6 GTP.With the simulation running,the rxdata is not consistent with the txdata for 8B10B error.Disparity error and not in table error occurs.
Here is my question.
Does the Xilinx GTP/MGT simulation model can simulate the bit error on the serial line or the error bit is added automatically by xilinx simulation model?
if it isn't automatic,where could be wrong?
I will be appreciate if anyone could help me.
Thanks in advance.
01-13-2015 12:59 AM
01-13-2015 06:51 AM
Thanks for you reply.
The V4-MGT's rxusrclk is derived for rxrecclk.Could this be the source of the question?
V4-MGT and S6-GTP are both sourced by the same reference clk in my testbench.So jitter is not the point.
"Please make sure that the GT settings for both S-6 and V-4 devices match as a first step."I think you mainly point to the clock match.Do I get your point?
Rxdata has been right for about 50 usrclk,then rxdata get inconsistent with txdata and signal associated with 8b10b decoder error get valid.In fact,the txdata is a PRBS generated by a LFSR. Does this affect in simulation?
Thanks for your help!
01-20-2015 12:55 AM