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lanhao1991
Contributor
Contributor
8,452 Views
Registered: ‎03-27-2014

rxdata error in GTP simulation using modelsim

Hi,everyone

 

I connect two Multi Gbit transceiver and  do a simulation using Modelsim .One is spartan6 GTP,the other is Virtex4 MGT.

At the beginning ,rxdata of MGT is consistent with the txdata of Spartan6 GTP.With the simulation running,the rxdata is not consistent  with the txdata for 8B10B error.Disparity error and not in table error occurs.

Here is my question.

Does the Xilinx GTP/MGT simulation model can simulate the bit error on the serial line or  the error bit is added automatically by xilinx simulation model?

if it isn't automatic,where could be wrong?

I will be appreciate if anyone could help me.

Thanks in advance.

 

Best regards

lan hao

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3 Replies
smarell
Community Manager
Community Manager
8,449 Views
Registered: ‎07-23-2012

The data errors- disparity and not-in-table errors are not intended.
Xilinx example design doesn't inject errors automatically.

Please make sure that the GT settings for both S-6 and V-4 devices match as a first step.
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lanhao1991
Contributor
Contributor
8,431 Views
Registered: ‎03-27-2014

 

 

 

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venkata
Moderator
Moderator
8,371 Views
Registered: ‎02-16-2010

Along with 8B10B errors, did you monitor any other status signals of Virtex-4 MGT?
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