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Visitor zc20060102
Visitor
4,198 Views
Registered: ‎12-14-2009

s3e ddr sdram controller design

Dear friends,

  I am a novice in EDA.I want to design a ddr sdram controller with my s3e board.

when I read some documents about it,problems  come across to me.

As I know,DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.

In my point of view,They are all edge-aligned when they come from controller or sdram and DQS will be phase shifted once enter  controller or sdram.Am I right?

I scan the programs which MIG creates,there are  programs named tap_dly and cal_ctl.They use the LUT to calibrate time delay.So how does it work?

Does any one knows?Thank you for you answer.

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2 Replies
Xilinx Employee
Xilinx Employee
4,175 Views
Registered: ‎10-23-2007

Re: s3e ddr sdram controller design

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Visitor zc20060102
Visitor
3,839 Views
Registered: ‎12-14-2009

Re: s3e ddr sdram controller design

thank you for your reply ! i have known the principle of ddr !

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