03-21-2010 09:06 PM
I am a novice in EDA.I want to design a ddr sdram controller with my s3e board.
when I read some documents about it,problems come across to me.
As I know,DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.
In my point of view,They are all edge-aligned when they come from controller or sdram and DQS will be phase shifted once enter controller or sdram.Am I right?
I scan the programs which MIG creates,there are programs named tap_dly and cal_ctl.They use the LUT to calibrate time delay.So how does it work?
Does any one knows?Thank you for you answer.
03-22-2010 10:34 AM
There is a bit of information on these pages:
I hope this helps.