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Visitor teerlinc
Visitor
7,467 Views
Registered: ‎12-09-2012

shift 3 BIN to BCD display problems

I am having a problem with a simple 8-bit input binary to bcd displaying to 7seg. I get the last number to display fine, but the first two remain dark.  For example 8-bit binary input of 11111111 should display 255 but I can only get the 5 to appear.

I have attached my current code. I thought at first that it was the clock but I cannot figure it out. 

Here is the code for the Seven segment display:

entity x7seg is
	port(
		x: in STD_LOGIC_VECTOR(15 downto 0);
		clk : in STD_LOGIC;
		clr : in STD_LOGIC;
		a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
		an : out STD_LOGIC_VECTOR(3 downto 0);
		dp : out STD_LOGIC
		);
end x7seg;

architecture Behavioral of x7seg is
 signal s: STD_LOGIC_VECTOR(1 downto 0);
 signal digit : STD_LOGIC_VECTOR(3 downto 0);
 signal aen : STD_LOGIC_VECTOR(3 downto 0);
  
begin

	
	dp <= '1';
	-- set aen(3 downto 0) for leading blanks
	aen(3) <= x(15) or x(14) or x(13) or x(12);
	aen(2) <= x(15) or x(14) or x(13) or x(12)
			or x(11) or x(10) or x(9) or x(8);
	aen(1) <= x(15) or x(14) or x(13) or x(12)
			or x(11) or x(10) or x(9) or x(8)
			or x(7) or x(6) or x(5) or x(4);
	aen(0) <= '1'; -- digit 0 always on
	
-- Quad 4-to-1 MUX: mux44
process(s,x)
begin
	case s is 
		when "00" => digit <= x(3 downto 0);
		when "01" => digit <= x(7 downto 4);
		when "10" => digit <= x(11 downto 8);
		when others => digit <= x(15 downto 12);
	end case;
end process;

--// 7-segment decoder: hex7seg
process(digit)
begin
	case digit is 
		WHEN X"0" => a_to_g <= "0000001";  -- 0
		WHEN X"1" => a_to_g <= "1001111";  -- 1
		WHEN X"2" => a_to_g <= "0010010";  -- 2
		WHEN X"3" => a_to_g <= "0000110";  -- 3
		WHEN X"4" => a_to_g <= "1001100";  -- 4
		WHEN X"5" => a_to_g <= "0100100";  -- 5
		WHEN X"6" => a_to_g <= "1100000";  -- 6
		WHEN X"7" => a_to_g <= "0001111";  -- 7
		WHEN X"8" => a_to_g <= "0000000";  -- 8
		WHEN X"9" => a_to_g <= "0001100";  -- 9
		WHEN X"A" => a_to_g <= "0001000";  -- A
		WHEN X"B" => a_to_g <= "1100000";  -- B
		WHEN X"C" => a_to_g <= "0110001";  -- C
		WHEN X"D" => a_to_g <= "0100010";  -- D
		WHEN X"E" => a_to_g <= "0110000";  -- E
		WHEN others => a_to_g <= "0111000";  -- F
	end case;
end process;

--Digit select: ancode
	process(s, aen)
		begin 
			an <= "1111";
			if aen(conv_integer(s)) = '1' then
				an(conv_integer(s)) <= '0';
			end if;
	end process;
	
-- 2-bit counter
	process(clk, clr)
	begin
		if clr = '1' then
		 s <= "00";
		elsif clk'event and clk = '1' then
			s <= s+ 1;
		end if;
	end process;
	

 Converter

entity BINtoBCD is
	port(
			b : in STD_LOGIC_VECTOR(7 downto 0);
			
			p : out STD_LOGIC_VECTOR(9 downto 0)
		 );
end BINtoBCD;

architecture Behavioral of BINtoBCD is

begin
	bcdl : process(b)
	
	variable z : STD_LOGIC_VECTOR(17 downto 0);
	
	begin
		
			for i in 0 to 17 loop
				z(i) := '0';
			end loop;
			
			z(10 downto 3) := b;
			
			for i in 0 to 4 loop
				if z(11 downto 8) > 4 then
					z(11 downto 8) := z(11 downto 8) + 3;
				end if;
				
				if z(15 downto 12) > 4 then
					z(15 downto 12) := z(15 downto 12) + 3;
				end if;
				
				z(17 downto 1) := z(16 downto 0);
			end loop;
			
			p <= z(17 downto 8);
		end process bcdl;

end Behavioral;

 and Top Level

entity BINtoBCD_Top is
	port(
		mclk : in STD_LOGIC;
		clr : in STD_LOGIC;
		btn : in STD_LOGIC_VECTOR(3 downto 3);
		sw : in STD_LOGIC_VECTOR(7 downto 0);
		ld : out STD_LOGIC_VECTOR(7 downto 0);
		a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
		an : out STD_LOGIC_VECTOR(3 downto 0);
		dp : out STD_LOGIC
		);
end BINtoBCD_Top;

architecture Behavioral of BINtoBCD_Top is
component BINtoBCD is
	port(
		b : in STD_LOGIC_VECTOR(7 downto 0);
		p : out STD_LOGIC_VECTOR(9 downto 0)
		);
end component;

component x7seg is
	port(
		x: in STD_LOGIC_VECTOR(15 downto 0);
		clk : in STD_LOGIC;
		clr : in STD_LOGIC;
		a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
		an : out STD_LOGIC_VECTOR(3 downto 0);
		dp : out STD_LOGIC
		);
end component;

COMPONENT ClkDiv
	PORT(
		mclk : IN std_logic;
		clr : IN std_logic;          
		clk : OUT std_logic
		);
	END COMPONENT;

signal clock : STD_LOGIC;
signal x : STD_LOGIC_VECTOR(15 downto 0);
signal p : STD_LOGIC_VECTOR(9 downto 0);

begin

-- concatenate zeros and output of BINtoBCD
x <= "000000" & p;
-- display binary value of switches on LEDs
ld <= sw;

B1: BINtoBCD
	port map(
		b => sw,
		p => p
		);
		
X2: x7seg
	port map(
		x => x,
		clk => clock,
		clr => clr,
		a_to_g => a_to_g,
		an => an,
		dp => dp
		);
		
X3: ClkDiv PORT MAP(
		mclk => mclk,
		clr => clr,
		clk => clock
	);
		
end Behavioral;

 The clock divider is attached.  This code is from a VHDL example book, I cannot, however, get this one to work. Any ideas what is missing?

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16 Replies
Teacher eilert
Teacher
7,455 Views
Registered: ‎08-14-2007

Re: shift 3 BIN to BCD display problems

Hi,

have you checked your code in a behavioral simulation?

There you could see misbehavior of internal signals much easier.

 

If you want to take a quick glance at the resulting value, you might comment out the digit blanking part and set aen to "1111" to enable all digits.  But I guess you will just see zeros there.

 

You should check your BCD converting process.

Since it is fully combinatorical you need to watch the variables change in their delta cycles.

Don't know about ISIM, but Modelsim can do that at least in the list window (maybe actual versions can do it in the waveform too).

 

btw: A loop for setting a SLV to zero?

         How about:

z := (others => '0');

 

Have a nice simulation

  Eilert

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Visitor teerlinc
Visitor
7,451 Views
Registered: ‎12-09-2012

Re: shift 3 BIN to BCD display problems

Thank you for your reply. All of the inputs come from the digilint BASYS board, so the simulation isn't very helpful. The binary to bcd converter came from my book. Also, the output always gives me the correct right hand number so it is clear that the converter is working, I am just having a problem with the first two digits on the seven segment display not displaying. If the decimal number is 128, I get 8 on the display, and 53... I only see the 3.

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Historian
Historian
7,442 Views
Registered: ‎02-25-2008

Re: shift 3 BIN to BCD display problems


@teerlinc wrote:

Thank you for your reply. All of the inputs come from the digilint BASYS board, so the simulation isn't very helpful.


You must learn how to write a proper test bench. And then simulation will be very helpful.

----------------------------Yes, I do this for a living.
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Visitor teerlinc
Visitor
7,438 Views
Registered: ‎12-09-2012

Re: shift 3 BIN to BCD display problems

My book doesn't say anything about test benches.  

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Historian
Historian
7,429 Views
Registered: ‎02-25-2008

Re: shift 3 BIN to BCD display problems


@teerlinc wrote:

My book doesn't say anything about test benches.  


That doesn't mean that a proper test bench is not important. It does mean that your book is incomplete.

A test bench is essentially. If you want to have a career in FPGA design then the sooner you learn about testbenches, the better.

See here, for example.

----------------------------Yes, I do this for a living.
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Visitor teerlinc
Visitor
7,424 Views
Registered: ‎12-09-2012

Re: shift 3 BIN to BCD display problems

Thank you for the resource, I will check it out. But, until then: as I understand, (The book says) that I cannot display all of the numbers at once, unles the clock is faster than my eye. Could it still be my clock that is causing a problem?

I am far from any career in this subject, as you can see. This is my first time. :-) But, I do want to understand.

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Historian
Historian
7,421 Views
Registered: ‎02-25-2008

Re: shift 3 BIN to BCD display problems


@teerlinc wrote:

Thank you for the resource, I will check it out. But, until then: as I understand, (The book says) that I cannot display all of the numbers at once, unles the clock is faster than my eye. Could it still be my clock that is causing a problem?

I am far from any career in this subject, as you can see. This is my first time. :-) But, I do want to understand.


You keep talking about some book, which you haven't named.

----------------------------Yes, I do this for a living.
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Teacher hgleamon1
Teacher
7,415 Views
Registered: ‎11-14-2011

Re: shift 3 BIN to BCD display problems

What is the input clock frequency? I see that it goes through (some horrible and large) fabric clock divider.

 

So, if you have been told by your magic book that you won't see all numbers if the clock is too slow, what frequency must it be?

 

More detail!

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor teerlinc
Visitor
7,411 Views
Registered: ‎12-09-2012

Re: shift 3 BIN to BCD display problems

Oh, thank you, everyone for your kind and generous replies. My magic book is called "Digital Design, Using Digilent FPGA Boards" by Richard E Haskell and Darrin M Hanna. The clock divider, if you look at it, shows that the frequency is q(17), or 190.73 hz. The code for this particular clock divider is on page 196, Section 7.4, Listing 7.18, you will have to contact the authors if you are curious about why the code is so long. The description of the codes I listed above are in chapter 5, the particular section I am using is 5.3, it is called "Code Converters".  I am using the shift and add 3 algorithm, and it is given in my magic book in exactly the form listed above. The algorithm works, the first two digits are not displaying. If there is any other way that I can help you, let me know.

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Teacher hgleamon1
Teacher
6,724 Views
Registered: ‎11-14-2011

Re: shift 3 BIN to BCD display problems

Ignoring for a moment the quality of the clock divider, what happens if you increase the frequency, i.e. take a lower order bit as an output? q(8) for example.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Teacher hgleamon1
Teacher
6,715 Views
Registered: ‎11-14-2011

Re: shift 3 BIN to BCD display problems

One other thing, how does the "clr" input get driven at the top level?

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Teacher eilert
Teacher
6,714 Views
Registered: ‎08-14-2007

Re: shift 3 BIN to BCD display problems

Hi,

you wrote:

"Also, the output always gives me the correct right hand number so it is clear that the converter is working."

 

Well, having just one of up to three digits right isn't really a good proof for a working algorithm.

 

I would argue the other way around:

Two of the digits come out wrong (probably as zeros) so your converter isn't working correctly.

 

Your multiplexing scheme for the displays is a little complicated, but should work.

The frequency should be a minor problem, since you can see one digit.

if your digit multiplexing would be too slow, you would see the digits hopping, and if it would be too fast, the displays might get dimmed down a little, but that happens only when you are in a range of over 1 KHz or more.

 

If you would follow my last advice to disable the digit blanking part, you can at least check if your multiplexing is working.

 

About the book you used:

From the title it seemed to be some guide how to do implementations on the BASYS board.

This is just one special part of digital and system design, which normally comes after the design phase and behavioral testing done with a testbench. So I'm not surprised that this book dosn't mention simulation.

Still, you should do simulations of your designs. Like the others said: It helps you understanding your code, and is extremely useful for debugging.

 

Have a nice simulation

  Eilert

 

 

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Teacher hgleamon1
Teacher
6,709 Views
Registered: ‎11-14-2011

Re: shift 3 BIN to BCD display problems

Hi,

you wrote:

"Also, the output always gives me the correct right hand number so it is clear that the converter is working."

This would indicate (to me, at least) that the signal s is stuck at "00" - a possible sign that the clr signal is still at '1'.

 

Of course, this would be obvious under simulation ...

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor teerlinc
Visitor
6,698 Views
Registered: ‎12-09-2012

Re: shift 3 BIN to BCD display problems

Thank you, everyone, for your unconditonal support.  I have fixed the problem, it was indeed a connection between the clock and the counter. The converter was not altered, it works perfectly, as suspected. 

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Highlighted
Newbie zgd2449
Newbie
6,634 Views
Registered: ‎04-04-2013

Re: shift 3 BIN to BCD display problems

If any one can help me to solve this problem please 

Develop a behavioral VHDL model of a synchronous (clocked) 2-digit, modulo-16 binary-coded-decimal (BCD) up counter. The counter should count from 0 up to 15 and then continue from 0 again. The counter should have an active high CLR signal to reset its contents to 0 at any time. The counter's state should be displayed on the 7-segment display module of the Nexys 2 Board. Both the CLK and the CLR signals should be mapped to pushbuttons, respectively. Note: when using signal CLOCK from a bush button for clocking your circuit you must add the statement NET "CLOCK" CLOCK_DEDICATED_ROUTE = FALSE; to your .ucf file. You should implement this counter using the FPGA, the 7-segment display and push-buttons on your Nexys 2 Board.
a) Turn in a hard copy of the .vhd and .ucf files for your design, respectively. 
b) Map your circuit to the Xilinx FPGA chip that is located on your FPGA
Development Board by running the Implement step. Before doing so, add a User
Constraints (.ucf) file to your project to make proper pin assignments for your
designs. The Master .ucf file for the Nexys 2 Board is available through the Class
Web Page. However, you need to edit it to keep only those signals that are defined in
your .vhd file. Turn in only the device utilization and used pin assignments
sections, respectively, of the Pad Report. 
Email : mass1311@yahoo.com

Tags (1)
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Explorer
Explorer
6,625 Views
Registered: ‎12-31-2012

Re: shift 3 BIN to BCD display problems

No one is going to do your homework for you. Figure it out, it's not hard. 

---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
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