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Observer
Observer
4,741 Views
Registered: ‎03-07-2016

sp605 aurora protocol

i need a example design of four lane aurora protocol for sp605

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

Please visit http://www.xilinx.com/products/boards-and-kits/device-family/nav-spartan-6.html  and check all the boards’ example reference.

 

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Moderator
Moderator
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Registered: ‎02-16-2010

The SP605 provides access to 4 MGTs.
• One (1) MGT is wired to the PCIe x1 Endpoint (P4) edge connector fingers
• One (1) MGT is wired to the FMC LPC connector (J2)
• One (1) MGT is wired to MGT SMA connectors (J36, J37)
• One (1) MGT is wired to the SFP Module connector (P2)

So you can test 4-lane aurora core in loopback mode.

Check XAPP1193 for guidance on what needs to be done to target the Aurora core to an evaluation board.
http://www.xilinx.com/support/documentation/application_notes/xapp1193-aurora-8b10b-on-kc705.pdf
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