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Visitor
Visitor
6,837 Views
Registered: ‎09-26-2009

spartan 3E XC3S100E write to memory problem

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 i am making a project where i am getting data. each data is equal to a memory address.i want to add 1 to each of this memory addresses

 the clock of the memory is twice fater then the clock of the data so i can get the value in this memory address and then add 1

 in the test bench i am sending data of a counter so every address should have value of 1

 the problem is the write takes me more time then the double rate clock period so i am ending with 1,2,3,4...N and not with 1 in every address

 i checked the frequency in wich the memory can work & it is about 150MHz. i am using a 50ns clock and half of this is the double clock rate and still i have the delay i mentioned

does any one have any idea why is that

 

 

thank for every body!!!

 

 

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Professor
Professor
8,641 Views
Registered: ‎08-14-2007

Can you post your code?  It sounds to me like you are not looking at the

read data on the correct clock cycle.  The incrementing pattern you

describe would happen if the Block RAM is running in the default mode

of write-first, and you are looking at the read data on the first of the

two cycles that your address is stable.  This would actually give you the

write data from the previous address due to the write-through logic

in the block RAM.  The read data is actually valid during the second

of the two cycles of valid address, so your addition needs to happen

combinatorially (without a clock delay).

 

Regards,

Gabor

-- Gabor

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Professor
Professor
6,827 Views
Registered: ‎08-14-2007

If you are using block RAM, you need to be aware that the memory has a register on the

read output so the old data comes out on the cycle after you apply the address.  Then

your addition needs to happen in the same clock cycle you write the memory back.  So

you have in one clock cycle: the clock to output time of the memory plus the combinatorial

delay of your adder and the setup time to write memory.  If you find that you need to pipeline

the addition to meet timing (I'm not sure you do at 25 ns) then you would need more clock cycles

or you need to change your approach to interleave read and write cycles from successive

data inputs.  I have used the latter approach on Virtex 5 at 200 MHz, so it shouldn't have

any problems in Spartan 3 at 40 MHz.  Still I'm a bit confused on your statement

 "the write takes me more time then the double rate clock period"

Is this in the real hardware or is your testbench showing you this during behavioral

simulation?

 

Regards,

Gabor

-- Gabor
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Visitor
Visitor
6,824 Views
Registered: ‎09-26-2009

first thank you for your time and knowledge

 

as an answer to your question i ment that i see that in test bench (behavioral imulation)

 

i think that you are right and it not supposed to be a problem to implement that in 40Mhz

 

( i check that with xilinx definitions )

 

regards

 

 Efi 

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Professor
Professor
8,642 Views
Registered: ‎08-14-2007

Can you post your code?  It sounds to me like you are not looking at the

read data on the correct clock cycle.  The incrementing pattern you

describe would happen if the Block RAM is running in the default mode

of write-first, and you are looking at the read data on the first of the

two cycles that your address is stable.  This would actually give you the

write data from the previous address due to the write-through logic

in the block RAM.  The read data is actually valid during the second

of the two cycles of valid address, so your addition needs to happen

combinatorially (without a clock delay).

 

Regards,

Gabor

-- Gabor

View solution in original post

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Visitor
Visitor
6,767 Views
Registered: ‎09-26-2009

just want to say TNX for your time

 

as you can see the problem was solved  THANKS

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Newbie
Newbie
5,266 Views
Registered: ‎01-30-2013
i (kamal) want to make my major project on fpga..my clg provided me xilinx spartan 3e xcs100e fpga board..so kindly help me in deciding topic of the project..
my email id is kamal.bhugra7@gmail.com
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