I am using spartan 3an xc3s700an 5-fgg484 starter kit with verilog HDL and i am trying to interface with on board ddr2 sdram. I am new in fpga but my project needs sdram. By the way the project is image processing(sensing emotions from face images). Although i am not using any memory to enderstand emotions, there is no enough space in FPGA to save the 400x400 photo and the processing units. So I have to do this interface. Interface will be simple. I do not need a lot of signals. Just vital signals.
The interface will write grayscale pixels (came from cmos camera) to ddr2 sdram and then i will read them from memory and do some manupulations on them and write them back into their old address.
I have decided to use MIG interface and I have tried to write control unit for that but I have failed. Now I am trying to use xilinx design which is in the spartan 3a starter kit sources. The design atteched.
Here is my problem. Design have chip scope signals and i think there is no need to remove them from the design. Synthesize is done with a lot of warnings but Translate have failed at implementing design step. There are ucf file errors and some of them is below.