We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor naizath
Registered: ‎06-25-2009

spartan 3e problem during place & route

I get this message while placing and routing

IO is using a clock buffer but it is not placed in GCLK or GCK type pin. Please move it to a GCLK or a GCK pin.


I do not know the GCLK or GCK pins in the spartan-3e board.

pls help


Tags (1)
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎01-03-2008

Re: spartan 3e problem during place & route

The Spartan-3E datasheet includes the pinout definitions for each package and the user guide for the boad that you are using should tell you which of these have been connected to an actual clock source.
Message Edited by mcgett on 01-09-2010 03:11 PM
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos