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fisher_ligang
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Registered: ‎01-24-2010

spartan6 SeletIO Interface Wizard,help me!!!

  HI.

  I would now like to achieve XCS6X ** T-2 and AD-chip interface, the AD output SDR clock, rate 800M, output data for the two-way LVDS signals.
Now I use "SeletIO Interface Wizard" to generate a 2 into 16 of the deserializer, the data clock constraint to the 800M, but the PAR only went 370M,
The design does not add additional logic, only call a "SeletIO IP".
I ask how can I solve this problem, XCS6X45T does not support "RocketIO IP" is calling the other IP, or only to replace faster FPGA?
If I binding was revised to 400M, PAR no timing error, but reporting the highest frequency is 370.370MHz.

thanks.

                                                                                              fisher_li

 

 

Source:


`timescale 1 ps / 1ps

module top_rx(
 DCLKP,
 DCLKM,
 DA_P,
 DA_M, 
 Rx_Clk,
 Rx_Dat0
 );
 
 input  DCLKP,
 DCLKM;       //800M
 
 input [1:0] DA_P;   //800M
 input [1:0] DA_M;   //800M
 
 output     Rx_Clk; //100M
 
 output [15:0] Rx_Dat0;
 
 parameter vcc = 1'b1;
 parameter gnd = 1'b0; 
 
 wire [15:0] DOUT0;
  
 assign Rx_Dat0    =  DOUT0;
 
 wire DCLK;
 
 SelectIO4 IO0( 
  .DATA_IN_TO_DEVICE  (DOUT0), 
  .CLK_DIV_OUT   (Rx_Clk),
  .DATA_IN_FROM_PINS_P  (DA_P),
  .DATA_IN_FROM_PINS_N  (DA_M),
  .CLK_IN_P   (DCLKP),
  .CLK_IN_N   (DCLKM),
  .CLK_RESET   (gnd),
  .IO_RESET   (gnd)
   );
  
  
endmodule

IP module:

module SelectIO4
   // width of the data for the system
 #(parameter sys_w = 2,
   // width of the data for the device
   parameter dev_w = 16)
 (
  // From the system into the device
  input  [sys_w-1:0] DATA_IN_FROM_PINS_P,
  input  [sys_w-1:0] DATA_IN_FROM_PINS_N,
  output [dev_w-1:0] DATA_IN_TO_DEVICE,
  input              CLK_IN_P,
  input              CLK_IN_N,
  output             CLK_DIV_OUT,
  input              CLK_RESET,
  input              IO_RESET);

800M Constraints:

NET "DCLKP" IOSTANDARD = "LVDS_33";
NET "DCLKP" IOSTANDARD = "LVDS_33";

NET "DA_P*" IOSTANDARD = "LVDS_33";
NET "DA_M*" IOSTANDARD = "LVDS_33";

NET "DCLKP" LOC        = "K21";
NET "DCLKM" LOC        = "K22";

NET "DA_P[0]" LOC      = "P20";
NET "DA_M[0]" LOC      = "N19";

NET "DA_P[1]" LOC      = "L20";
NET "DA_M[1]" LOC      = "L22";

NET "IO0/clk_in_int" PERIOD = 800.0 MHz;

PIN "IO0/clkdiv_buf_inst.O" CLOCK_DEDICATED_ROUTE = TRUE;


Derived Constraint Report
Derived Constraints for IO0/clk_in_int
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|IO0/clk_in_int                 |      1.250ns|      2.000ns|      0.338ns|            1|            0|            0|            0|
| IO0/clk_in_int_buf            |      1.250ns|          N/A|          N/A|            0|            0|            0|            0|
| IO0/clk_div                   |     10.000ns|      2.700ns|          N/A|            0|            0|            0|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.

Timing summary:
---------------

Timing errors: 1  Score: 750  (Setup/Max: 0, Hold: 0, Component Switching Limit: 750)

Constraints cover 0 paths, 0 nets, and 0 connections

Design statistics:
   Minimum period:   2.700ns{1}   (Maximum frequency: 370.370MHz)
  
  
  
 400M Constraints:
 
 .....
 NET "IO0/clk_in_int" PERIOD = 400.0 MHz;
 ......
 

 Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 0 paths, 0 nets, and 0 connections

Design statistics:
   Minimum period:   2.700ns{1}   (Maximum frequency: 370.370MHz)

Message Edited by fisher_ligang on 01-27-2010 06:30 PM
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fisher_ligang
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Registered: ‎01-24-2010

Help me..............
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