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Visitor xianrenwang
Visitor
8,669 Views
Registered: ‎11-16-2011

spartan6 coregen IP, implement ERROR

I use spartan6 LX45T FGG484,when I use 1DUAL, 2GTP, functional is OK. When I  to generate a 2 DUAL, 4GTP,then implement, is error. Error message is below.

4GTP used one OSC, and bypass RX buffer and TX buffer. each rx clk used a BUFIO2 and BUFIO2FB. how can i do.

 

 

 

 

捕获1.PNG

捕获1.PNG
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Visitor xianrenwang
Visitor
8,269 Views
Registered: ‎11-16-2011

Re: spartan6 coregen IP, implement ERROR

My FPGA is spratan6 lx45t FGG484, I want 4lane GTP , which rx buffer and tx buffer is all bypass, when coregen finish, used the example to implement. I change nothing, Example implement is error. How can I get help. 

                                                                                            Thank you 

 

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Visitor xianrenwang
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8,193 Views
Registered: ‎11-16-2011

Re: spartan6 coregen IP, implement ERROR

the 4lane coregen's example to implement ERROR, nobody can solve?

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