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Explorer
Explorer
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Registered: ‎05-31-2015

std_logic_vector to sfixed

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Hello,

 

               I am doing some fixed point operation. I have a 24 bit std_logic_vector as input to module. I want to convert this to sfixed datatype. Which function can I use for this ? Or what are the options for such an implementation. I am working in VHDL in Xilinx ISE 14.7.

 

With Regards

Shalini

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Explorer
Explorer
10,463 Views
Registered: ‎05-31-2015

Hello,

           I changed std_logic_vector to integer using to_integer(signed(stdlogicvector)). Then I changed this integer to sfixed using to_sfixed(integer,num1,num2).

 

With Regards

Shalini 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

refer language template

https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_language_templates.htm

 

check this as well

http://vhdlguru.blogspot.in/2010/03/fixed-point-operations-in-vhdl-tutorial.html

http://stackoverflow.com/questions/34349367/using-fixed-point-in-vhdl

Thanks and Regards
Balkrishan
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Explorer
Explorer
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Registered: ‎05-31-2015

Hello,

 

           Thanks for reply. I reffered them , but my issue still persist. Please help.

 

With Regards

Shalini

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Highlighted
Explorer
Explorer
10,464 Views
Registered: ‎05-31-2015

Hello,

           I changed std_logic_vector to integer using to_integer(signed(stdlogicvector)). Then I changed this integer to sfixed using to_sfixed(integer,num1,num2).

 

With Regards

Shalini 

View solution in original post

0 Kudos