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Teacher eteam00
Teacher
17,460 Views
Registered: ‎07-21-2009

understanding BITSLIP (one more time)

UPDATED 02-dec-2010:  Replaced all references to DIVCLK with CLKDIV.  Both terms are used in UG382 (Clocking Resources), but only CLKDIV is used in UG381 (SelectIO Resources) and DS162 (Datasheet).  All my other posts in this thread have been updated as well.

 

This is my latest attempt to make sense of the Spartan 6 ISERDES2 BITSLIP function.  It probably isn't all that complicated, but its simplicity is obscured by inconsistencies and omissions in the Xilinx documentation, plus Xilinx' reluctance to provide details of the BITSLIP function logic.  Even the webcase support on BITSLIP function has been clouded by an uneven understanding of the function by the support team.  Roy (as in roym) has an understanding of ISERDES2 and BITSLIP which is as deep and thorough as anyone else I've engaged on the Xilinx team.

 

So, here is my unofficial and unsanctioned description of the BITSLIP function.

 

Comments, additions, corrections, and questions are welcome.

 

- Bob Elkind

 

Diagrams:

 

 

my corrections (markups) to UG381 Figure 3-1:

UG381 Fig 3-1 markup.jpg

 

 

My attempt at reverse-engineering the BITSLIP 'black box':

bitslip functional diagram.JPG

 

 

My markups and corrections to UG381 Figure 3-2 (not very useful, but it corrects some misinformation)

UPDATED 23-Nov  Changed lines 3,5,7, & 9 to make bit numbering and ordering consistent with Fig 3-1:

UG381 Fig 3-2 markup v3.jpg



OK, now for the text (BITSLIP 101):

 

Word framing of deserialised data can be slow and resource-hungry when implemented in the parallel (word) domain.  If implemented in the bit-serial domain, word framing can be extremely compact.  The ISERDES2 block has provisions for word framing in the serial domain, within the ISERDES2 block.   This feature is called BITSLIP.

 

First, let's describe the problem of word framing at bit-serial data rates.  Input serial data streams up to 1Gb/sec (per pin) are supported by Spartan 6.  The IO logic which supports such data rates requires a matching high-frequency clock, called IOCLK, which is derived from the serial input signals to the FPGA.  To handle thes high data rates, the Spartan 6 IO circuitry is designed to operate at much higher frequencies than the bulk of the FPGA logic (i.e. the fabric).  The upper limit for fabric clock frequency is much lower than the IOCLK frequency limit.  Data decoders, used for detecting proper word framing in parallel data words, are built in the (slower) FPGA fabric logic.  Constrained to operating at fabric clock speed, word framing logic often cannot directly control the serial-rate logic in the IO section.  Word framing logic needs some help to control the deserialiser blocks.

 

The BITSLIP function includes logic to accept a control signal generated in the FPGA fabric by parallel word logic running at parallel word clock rates.  Inside the BITSLIP function, the slow input control signal is synchronised to the IOCLK (bit rate) clock, and is used to accomplish word framing.

 

To see how BITSLIP works, first look at the ISERDES2 block diagram (Fig 3-1).  Register B is nothing more than a single IOCLK delay register fed by serial-bit-rate shift register Register A.  When the BITSLIP function is enabled (see UG381 Table 3-2, ISERDES2 Attributes), however, Register B becomes register which samples new data only once every N clock cycles (where N is the parallel word bit-width of the ISERDES2 output).  This slows the output of Register B to word-rate (rather than bit-rate).

 

If Register B samples precisely on word boundaries, the output of Register B will be correctly word-framed.  BITSLIP is designed to delay the update of Register B, under fabric (user logic) control, until the output of Register B is correctly word-framed.

 

To see how BITSLIP manages the update of Register B, now look at the Functional Diagram of ISERDES2 BITSLIP function.  The output of the BITSLIP function is the clock enable for ISERDES2 Register B.  When the clock enable is asserted, Register B inputs are sampled.  When the clock enable is de-asserted, Register B does not change.  The Modulo N counter in the diagram counts at IOCLK rate, from 0 to N-1.  When the counter value is 0, the Register B clock enable is asserted.  The counter wraps around from (N-1) to 0, and Register B updates once per N clock cycles -- once per word.

 

This is all well and good as long as the BITSLIP clock enable output (and Register B input sampling) coincides with the boundary from one data word to the next.  Otherwise, the timing of the BITSLIP output clock enable must somehow be changed to align with data word boundaries.  The rest of the BITSLIP logic allows the BITSLIP control input to delay the clock enable output under fabric control, until the clock enable output occurs at the correct word boundary (and word framing will be correct).

 

To shift the position of the clock enable output, fabric logic asserts the BITSLIP control input.  Inside the BITSLIP block, the BITSLIP input is sampled on the rising edge of CLKDIV.  CLKDIV is a word-rate clock, and is presumed to be a copy of the fabric clock which generates the BITSLIP control input.  Because the BITSLIP control input is sampled by CLKDIV inside the BITSLIP block, the timing requirements for the BITSLIP input are very modest.  The minimum required setup and hold times, referenced to the CLKDIV rising edge, are listed in the Spartan 6 datasheet DS162.

 

Inside the BITSLIP block, the sampled BITSLIP control input is then ANDed with a positive CLKDIV edge detection, and re-sampled at IOCLK frequency.  This re-sampled control is used to insert one (and only one) extra IOCLK clock cycle in the Modulo [N or N+1] word cycle.   The Modulo [N or N+1] counter takes N+1 (instead of N) IOCLK cycles to complete a full cycle.  This delays the BITSLIP clock enable output (to Register B) one IOCLK cycle, and effectively shifts the output of Register B a single bit position left.  If the BITSLIP control input remains asserted for a second CLKDIV rising edge, the word framing will shift again.  After N-1 shifts, the result will be the same as a single bit-position shift to the right.  After N shifts, the result will be the same as 0 shifts (no change).

 

The assertion of the BITSLIP control signal will allow the word framing to change by only one bit position, no more than once per word.

 

To sum, BITSLIP performs word framing very compactly, at the cost of a handful of FFs and gates.  By comparison, a fabric word frame design requires an NxN barrel shifter, consuming considerably more logic and interconnect resources than the BITSLIP design to perform an equivalent function.

 

- Bob Elkind

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18 Replies
Moderator
Moderator
17,399 Views
Registered: ‎07-30-2007

Re: understanding BITSLIP (one more time)

This looks like a clear description to me, but I must say I think the description in the User Guide is OK too, especially with the pending modifications. 

 

From a functional point of view, it seems a little easier for me to look at the function of the bitslip like a counter driving a look up table with bitslip as another input.  When bitslip is low the LUT outputs a reset to the counter at N-1 and when it is high it uses N. A simplified model would look something like this:

 

   always @(posedge CLK0)
    begin
        if (shipParallel)
            cnt <=0;
        else 
            cnt <= cnt+1;
        if (cnt==4'h2 && !BITSLIP)
            shipParallel <= 1'b1;
        else if (cnt==4'h3 && BITSLIP)
            shipParallel <= 1'b1;
        else
            shipParallel <= 1'b0;
    end

 

This would be for the N = 4 case.

 

From a design point of view, though, I don't think it's necessary to know the internals of the bitslip.  Between the timing diagrams and the behavioral and post-route simulations one should be able to put a good design together.

 

--Roy

 

 

Roy


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Teacher eteam00
Teacher
17,380 Views
Registered: ‎07-21-2009

CORRECTED: understanding BITSLIP (one more time)

Roy,

 

1.  A problem with your 'simplified model' is that it suggests BITSLIP is sampled by CLK0 (IOCLK).  This contradicts the datasheet, which expresses BITSLIP setup/hold timing requirements referenced to CLKDIV (not IOCLK).  Fabric logic would have a difficult time ensuring setup and hold time relative to CLK0 (i.e. IOCLK).  If your example code is correct, you've just opened a nasty can of worms.

 

1.a  Your example code generates a one-time displacement of 'shipParallel'.  This will result in a shipParallel pulse 5 cycles from the previous pulse and 3 cycles from the following pulse.  In order to work correctly, BITSLIP must force the cnt counter to extend to a value of 4 (rather than 3) before wrapping back to 0.

CORRECTION:  My reading of Roy's code was incorrect on this point.   Please disregard "1.a".  - Bob

 

1.b  Your example code is likely to occasionally generate either 0 shipParallel pulses or a double pulse (2 consecutive IOCLK cycles), depending on the timing of BITSLIP from the fabric with respect to the cnt cycle.

 

2.  If you look at the markups to UG381 Figures 3-1 and 3-2, those markups (hopefully) correct a few instances of fundamentally misleading information.  The current BITSLIP description in the User Guide is vague enough to let these two diagrams (with the misleading information) seem plausible.  The combination of misleading diagrams and non-concise text description is (my opinion) 'fatal'.

 

3.  When I raised the concerns I had in a webcase, I was given incorrect information.  It wasn't until I referred to the webcase response in a forum posting that you caught the error and corrected it, for which I am quite grateful.  That forum exchange was 5 months ago.

 

4.  We users can't comment on the pending modifications to the User Guide, of course, based on either content or timing of its availability.  Which is one of the biggest reasons for my posting this thread.

Between the timing diagrams and the behavioral and post-route simulations one should be able to put a good design together.

5.a  As already mentioned, the diagrams (timing and block) in UG381 v1.3 are incorrect.

 

5.b  There is no timing diagram or block diagram for ISERDES2 in DDR mode (yet).

 

5.c  We could have a lively debate on the principle of depending on logic models (and simulation) as first-line user documentation.  Let's put it this way:  simulation is only as good as the models, the user, and the scope/breadth of the testbench.  Knowing in advance where to focus your (simulation) attention is a big part of successful testbench/simulation.  Depending on behavioural model and simulation is arguably the same as placing a very small needle in a very large haystack without so much as a prior warning to look for a needle in the first place.

 

I respect your knowledge and technical insight.  In this case, however, our differing perspectives remain a point of respectful disagreement.

 

-- Bob Elkind

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Moderator
Moderator
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Registered: ‎07-30-2007

Re: understanding BITSLIP (one more time)

If your example code is correct, you've just opened a nasty can of worms.

 

My example code was aiming at a functional description of the Block as derived from the user guide.  As noted it was simplified and dealing with the clkdiv alignment was the simplification as I didn't think it added to the understanding of bitslip as a whole. 

 

-Roy

Roy


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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

next question on BITSLIP timing

Roy (or others),

 

DS162 v1.10 (S6 datasheet) is the only doc which mentions timing requirements for BITSLIP control signal, referenced to CLKDIV.  The timing spec references CLKDIV, but doesn't specify which edge of CLKDIV should be respected.

 

Can you clear up this missing detail?  I'm sure it's likely to be the rising edge of CLKDIV, but gaining certainty on the matter is worth pursuing (especially if my assumption is incorrect).

 

Thanks,

 

Bob Elkind

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Moderator
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Registered: ‎07-30-2007

Re: next question on BITSLIP timing

Hi Bob,

I don't have an answer yet to the latest but let me talk about 1a and b just a minute.

 

 I was looking for 4 cycles 0-2 are 3 and reset is the fourth unless bitslip is high.

 

Attached is a simulation of the ckt.  Please don't hold me up on the CLKDIV and bitslip timing I didn't take the time to adjust precisely.  I just wanted to illustrate the concept.

 

I think what we are getting stuck on is Functional vs full circuit.  We are trying to show the functional timing and then Xilinx will guarantee the output if you use the "approved" clocking structure.  The idea is to free designers from having to know all the internals of the SERDES circuits (not to mention those nasty cans of worms). 

 

-Roy

Roy


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bitslip.jpg
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Teacher eteam00
Teacher
17,334 Views
Registered: ‎07-21-2009

cleanup details for BITSLIP

Here's a couple of document cleanup requests:

 

UG381 v1.3, Table 3-2

The description of the BITSLIP_ENABLE attribute includes the following:

The number of bits slipped is a function of the DATA_WIDTH selected.

This is useless at best, misleading at worst.  A single BITSLIP 'command' will cause a SINGLE bit position slip, regardless of selected DATA_WIDTH.


Next one is cleanup of a few misleading booboos in Figure 3-3
Updated to add consistency with Fig 3-1 in bit numbering

UG381 Fig 3-3 markup msb first.jpg

 

 

-- Bob Elkind

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

REVISED: next question on BITSLIP timing

Roy,  thanks for the followup.

 

My comments:

... let me talk about 1a and b just a minute...

My 1b critique was written before understanding that you had 'simplified' your example code to omit CLKDIV sampling the BITSLIP input.  This makes all the difference in the world for "1" and "1b" items.  You 'freed me' from 'having to know' about this without prior warning!  :)

I was looking for 4 cycles 0-2 are 3 and reset is the fourth unless bitslip is high.

Right, your sim waveforms show the 'sticky' displacement of shipParallel, rather than a one-time displacement.  Your original 'simple model' code wouldn't match this, but the bitslip behavioural model should.  This takes care of item '1a'.  Adding the cnt value to the sim traces would make this clear, but the position of shipParallel is clear enough evidence of 'doing the right thing'.

 

CORRECTION:  I am mistaken, Roy's original code works correctly.  Sloppiness on my part. - Bob

ANOTHER CORRECTION:  It looks like there is a possible 'hole' in Roy's code if BITSLIP input changes state when cnt==2.  The result would be either a missing shipParallel pulse (bad!), or a double shipParallel pulse (probably recoverable).

The idea is to free designers from having to know all the internals of the SERDES circuits...

Eyes rolling, Roy!  Sometimes ignorance is bliss, sometimes knowledge is power.

 

-- Bob Elkind

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

RETRACTED: updated my reverse engineered BITSLIP function diagram

Roy (and others),

 

I updated the 'reverse engineered diagram for the BITSLIP function', to more closely reflect RoyM's code model.  Scroll back to the original post in this thread, and you'll see the updated diagram.

 

Update 11/20/2010  I believe there's a bug in RoyM's model.  I hope it isn't reflective of the ISERDES2 design.  I've reverted to my original functional diagram of BITSLIP, in the first post of this thread.

 

- Bob Elkind

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Moderator
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Registered: ‎07-30-2007

Re: cleanup details for BITSLIP

 

Regarding Figure 3-3, I think it all hinges on whether the input is the MSB or LSB.  In Figure 3-1 the data is fed into the top flop which corresponds to Q4 on the output which I would like to call MSB and that is the way it is shown in XAPP1064 as well.  If that is the case then the direction of the bitslip in the Figure is correct.  That said, I can't think of a reason off the top of my head why you couldn't choose to call it LSB and have Q4 be the LSB output bit.  I would suggest naming the input D to correspond to the name on the ISERDES2 module. 

 

>  The number of bits slipped is a function of the DATA_WIDTH selected.

I will request a change to this wording.

 

I don't want to belabor it, but that was a simulation of the original model.

 

-R

Roy


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Teacher eteam00
Teacher
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Re: cleanup details for BITSLIP

Regarding Figure 3-3, I think it all hinges on whether the input is the MSB or LSB.

Actually, my first impression of Figure 3-3 was that the 2nd row referred to the INPUT of the first Register A flop rather than the OUTPUT of that flop.  What would be your understanding of "Frame Input Serial Data"?

 

And secondly, I inferred LSB from data values marked in the "Parallel Register B" row.  The most recently received bit is placed at the right (rather than left) end of the 4-bit value.  Considering this position the LSB is quite natural.

 

UPDATE:  I've incorporated Roy's comment on MSB vs. LSB to the Figure 3-3 diagram.  You can see the updated diagram in this thread, 4 posts up from this one.  These latest markups make the bit ordering of Parallel Register B line more clear, and make them consistent with Figure 3-1.  Same applies to the second row of Fig 3-3.

 

ELBOW NUDGE:  While we're on the subject, what is the likelihood of inserting a reference to either positive or negative CLKDIV edge, either in DS162 or UG381, thereby clarifying the timing requirement for the BITSLIP input ?

 

- Bob Elkind

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Teacher eteam00
Teacher
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Re: cleanup details for BITSLIP

I don't want to belabor it, but that was a simulation of the original model.

You are right, I was wrong.  Thank you for your persistence.

 

If I can have this much trouble with something small and simple, I can imagine how difficult it is to get something as complex as ISERDES2 mostly right on the first or second revision.  This also underscores the importance of having more than just one or two people reviewing a complex technical document.

 

- Bob Elkind

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Re: cleanup details for BITSLIP

 

> Actually, my first impression of Figure 3-3 was that the 2nd row referred to the INPUT of the first Register A flop rather than   the OUTPUT of that flop.  What would be your understanding of "Frame Input Serial Data"?

And secondly, I inferred LSB from data values marked in the "Parallel Register B" row.  The most recently received bit is placed at the right (rather than left) end of the 4-bit value.  Considering this position the LSB is quite natural.

 

I see your point but I don't think of the most recent as being on the right or left.  It gets it position from the framing.  Your method would lead to calling Q4 the LSB and I that would bother me.  The hardware will allow you to do it either way and the documentation is consistent the way it is. 

 

-R 

 

 

 

Roy


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Teacher eteam00
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Re: cleanup details for BITSLIP

I see your point but I don't think of the most recent as being on the right or left.  It gets it position from the framing.  Your method would lead to calling Q4 the LSB and I that would bother me.

I removed the "LSB" reference in the latest revision of my markup (7 posts up/back in this thread).  Hopefully all remaining ambiguity has been purged from the marked up diagram (of Figure 3-3).  Thank you for correcting my corrections!

... the documentation is consistent the way it is.

As a design engineer, a customer, and one who has read the stuff, I respectfully disagree.  The orginal motivation for this thread was filling in the missing information (e.g. BITSLIP funct diagram), but the rest of this thread has dealt in large part with cleaning up inconsistencies and other ambiguities.

 

If more and more detail is omitted, at some point inconsistencies become unachievable (pardon the rhetorical excess).   If it's confusing (and incomplete and ambiguous) to me, am I wrong?  If I am wrong, for whom are these documents written?

 

- Bob

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Teacher eteam00
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Re: cleanup details for BITSLIP

If more and more detail is omitted, at some point inconsistencies become unachievable (pardon the rhetorical excess).   If it's confusing (and incomplete and ambiguous) to me, am I wrong?  If I am wrong, for whom are these documents written?

As I read what I've written, it comes across as a bit combative and evocative of frustration (if not whiny).  My frustration is not aimed at Roy, who has been very patient and understanding.  Roy is, in large part, the messenger -- and as such he is doing a (sometimes) thankless job.

 

I started this thread out of both frustration and interest in making some sense of the complex stew of vague and conflicting information.  For the most part, I think the thread been pushed about as far as we can manage from within these forums.  I hope someone - anyone - finds this useful.

 

- Bob Elkind

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Observer gdowg
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Registered: ‎06-03-2009

Re: cleanup details for BITSLIP

Roy and Bob,

Seems like you guys have quite an interesting dicussion going about several topics caused by the digging into the BitSlip, but just thought I'd throw in my 2 cents about the LSB/MSB detail. Also, thanks for helping in the previous post.

 

It was necessary for me to look at Table 3-3 and Figure 3-1 (SelectIO UG381) in order to come to the conclusion the meaning of MSB/LSB in relation to the Q4,Q3,Q2,Q1 output of the ISERDES2. I think everyone would agree that MSB/LSB can be ambiguous. Anyway, if you only look at Table 3-3 you don't know what LSB means, actually phrases like  "1st bit received on wire" or "Last Bit Received" needs to be mentioned in order to define what you mean by MSB/LSB. Of course, looking at Figure 3-1 you can see that the first bit received should get shifted down and thus be Q1 which is refered to as LSB and doing a simple test with a known bit pattern would solve this trivial problem. But, adding a sentence to define what you mean by MSB/LSB can be helpful to a 1st time reader of the doc.

 

Extra Side Note:

For my case, my head was spinning because my device that I was communicating with was set to MSB First, in other words, the MSB of my meaning full data word was the first bit on the wire, which would then correspond to LSB for the SERDES.

 

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Re: cleanup details for BITSLIP

@gdowg

It was necessary for me to look at Table 3-3 and Figure 3-1 (SelectIO UG381) in order to come to the conclusion the meaning of MSB/LSB in relation to the Q4,Q3,Q2,Q1 output of the ISERDES2.

Unfortunately, Figures 3-1 and 3-3 are not consistent in bit numbering or ordering.  See the 7th post in this thread, my markups of UG381 Fig 3-3.  Some of the markups specifically address bit numbering/ordering, clearing up errors and ambiguity, and making Fig 3-3 consistent with Fig 3-1.

 

@ everyone

 

I've updated my marked up Fig 3-2 diagram, embracing "truth in bit numbering".  In the revised diagram, lines 3,5,7, and 9 are now ordered consistently with Fig 3-1 and my markups to Fig 3-3 -- and bit numbers are added (instead of leaving them to the imagination of the reader).  The first post in this thread now incorporates this latest diagram version.

 

I'm keeping my fingers crossed for the user guide update.

 

- Bob Elkind

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Comments on new UG388 rev. 1.4

UG388 Rev 1.4 has just been posted, and here are my quick comments and critiques in context below, in colour.  Overall, a mixed bag (some valuable improvements, but not enough to stop me from whining).

@eteam00 wrote:

 

Diagrams:

 

my corrections (markups) to UG381 Figure 3-1:

UG381 Fig 3-1 markup.jpg

Comment on Figure 3-1 in revision 1.4

 

  1. IOCLK connection to BITSLIP black box is still missing.
  2. CLKDIV connection to BITSLIP black box is still missing
  3. Erroneous connection of CE0 to BITSLIP black box hasn't been removed
  4. Numerous signal naming additions and corrections have been made
  5. Title has been updated to reflect "SDR mode"

 

 

My attempt at reverse-engineering the BITSLIP 'black box':

bitslip functional diagram.JPG

 

A block diagram (example above) describing operation of BITSLIP logic is still missing from the document.

 

My markups and corrections to UG381 Figure 3-2 (not very useful, but it corrects some misinformation)

UG381 Fig 3-2 markup v3.jpg

Comment on Figure 3-2 in revision 1.4

  1. Data values and bit ordering which make operation unambiguously clear are still missing
  2. Waveform previously labeled BITSLIP INPUT has been corrected to Internal Bitslip Clock Enable
  3. BITSLIP input waveform, describing timing relationship to CLKDIV, is still missing.
  4. CLKDIV waveform is still erroneously labeled GLOBAL CLOCK
  5. Parallel Register C transition is still misplaced by one IOCLK cycle

 


UG381 Fig 3-3 markup msb first.jpg


Comment on Figure 3-3 in revision 1.4

  1. No changes to Figure 3-3 (from revision 1.3) noticed.
  2. Without bit numbering, the diagram is ambiguous to the point of uselessness.
  3. The waveform (still) incorrectly labeled Frame Input Serial Data should be labeled Register A<4>

 

And one last ARGHHH! comment:

  • Why is the timing relationship between BITSLIP input and CLKDIV never mentioned?  This is absolutely critical information.

 - Bob Elkind

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Teacher eteam00
Teacher
8,890 Views
Registered: ‎07-21-2009

Two more BITSLIP issues

These are both slam-dunk easy questions to answer, but they should be cleared up.

 

1.  Yes or No:  BITSLIP enabled requires BOTH of the following:

  • CLKDIV input (BITSLIP is sampled by CLKDIV clock input)
  • ISERDES2 configured for either NETWORKING_PIPELINED or RETIMED interface_type

The right answer is clearly YES.  This is my sneaky and backhanded way of pointing out that in UG381 (v1.4), nowhere in the document is it clearly stated thay CLKDIV is required for BITSLIP operation.  On page 81, it is made clear that NETWORKING_PIPELINED and RETIMED Modes both support the use of BITSLIP.  This is OK for RETIMED mode, which clearly requires CLKDIV input clock.... but this is misleading (by omission) for NETWORKING_PIPELINED mode.

 

There are no diagrams, text, attribute tables, or signal tables in UG381 which spell out that even though CLKDIV isn't required for NETWORKING_PIPELINED mode, CLKDIV is required for using BITSLIP in NETWORKING_PIPELINED mode.

 

My humble request is that UG381 table 3-1 be updated to include implications and requirements (suggested wording below):

 

CLKDIV   Input    Global clock network input. This is the clock for input data

                  and control signals from the FPGA logic domain.  Required for

                  BITSLIP function and required for Phase-Detector logic.

 

BITSLIP  Input    Invoke Bitslip when High. Synchronous to CLKDIV. Bitslip operation

                  can be used with any DATA_WIDTH, cascaded or not.  Requires CLKDIV

                  input clock. Sampled on rising edge of CLKDIV input clock.

 

My next humble request is that UG381 Figure 3-1 be updated to show BITSLIP LOGIC block using (and requiring) CLKDIV input clock.

 

My 3rd next humble request is that UG381 sections for Bitslip Operation (version 1.4: page 82) and Phase Detector Overview (page 84) include mention of the requirement for a CLKDIV input clock.

 

My next question is less sneaky.

 

2.  Yes or No:  BITSLIP may be asserted on consecutive CLKDIV cycles.

 

Ordinarily, absent directions to the contrary, it should be assumed that the answer to this question is YES.  I honestly have not seen any text in UG388 which suggests that BITSLIP may NOT be asserted on consecutive CLKDIV cycles.  But the question is raised by flimsy association and flimsy circumstantial "evidence":

 

  • The apnotes which use BITSLIP (XAPP1064 and XAPP 495) show BITSLIP generated by state machines which do not assert BITSLIP for more than a sincle CLKDIV cycle.  Intentional or coincidental?
  • BITSLIP may not be asserted for consecutive CLKDIV cycles in Virtex 6 designs (UG361 v1.3, page 142).  Does the Spartan 6 acorn fall far enough from the Virtex 6 tree?
  • The BITSLIP logic inside the ISERDES2 block remains shrouded in secrecy.  Always assume the worst!

It would be wonderful to clear up these two questions for the forum audience (we are truly blessed!), and add these items to the edits queue for UG381 version 1.5

 

- Bob Elkind

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Summary:
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2. Search the forums (and search the web) for similar topics.
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