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Observer anassamir
Observer
7,063 Views
Registered: ‎04-19-2011

unrouted Signal

Good Morning everyone,

Im trying to use some logic beside my Giga speed serializer and the trigger of this logic is a signal from the clock generator of the serializer "ioclk" which is a 1Ghz clock......the problem is that when i try to put this signal "ioclk" in the process brackets as the trigger,i get an error in the place and route stage as follows :

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the   design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.   To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: ioclk pin:  buffers/I0 

Im using a a Spartan-6 FPGA LX45T CSG324  .........

any clue how could i resolve this?

Thanks alot in advance,
Anas 

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7 Replies
Observer anassamir
Observer
7,061 Views
Registered: ‎04-19-2011

Re: unrouted Signal

This is the VHDL code of the whole block and the process attached to the end....:

 

 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

library unisim ;
use unisim.vcomponents.all ;






entity testHighSpeedSer_oneFile is generic 

(
	D			: integer := 1 ;
	PLLD			: integer := 1 ;				-- Parameter to set the division factor in the PLL
	PLLX			: integer := 20 ;				-- Parameter to set the multiplication factor in the PLL
	S			: integer := 8 ;				-- Parameter to set the serdes factor 1..8
	CLKIN_PERIOD		: real := 20.000 ;				-- clock period (ns) of input clock on clkin_p
	DIFF_TERM		: boolean := FALSE) ;
 
 
 Port ( 
	        clk_50mhz : in  STD_LOGIC;
--           GigaData  : in std_logic_vector(7 downto 0);          		 
			  Pout : out  STD_LOGIC;
           Nout : out  STD_LOGIC);


end testHighSpeedSer_oneFile;



architecture Behavioral of testHighSpeedSer_oneFile is

-- Clock generator signals

signal 	clkintb			: std_logic ;			--
signal 	dummy			: std_logic ;			--
signal 	pllout_xs		: std_logic ;			--
signal 	pllout_x1		: std_logic ;			--
signal 	pll_lckd		: std_logic ;			--
signal 	gclk_int		: std_logic ;			--
signal 	buf_pll_lckd		:std_logic ;
signal   ioclk			:  std_logic ;             			-- ioclock from BUFPLL
signal	serdesstrobe		:  std_logic ;             			-- serdes strobe from BUFPLL
signal	gclk			:  std_logic ;             			-- global clock output from BUFG x1
signal	bufpll_lckd		:  std_logic;


-- Serializer signals


signal	txioclk			:  std_logic ;				-- IO Clock network
signal	txserdesstrobe		:  std_logic ;				-- Parallel data capture strobe
signal	reset			:  std_logic ;				-- Reset

signal	datain			:  std_logic_vector(7 downto 0) ;  	-- Data for output
signal	dataout_p		: std_logic_vector(0 downto 0) ;		-- output
signal	dataout_n		: std_logic_vector(0 downto 0) ;		-- output
signal	cascade_di 	: std_logic_vector(D-1 downto 0) ;
signal	cascade_do 	: std_logic_vector(D-1 downto 0) ;
signal	cascade_ti 	: std_logic_vector(D-1 downto 0) ;
signal	cascade_to 	: std_logic_vector(D-1 downto 0) ;
signal	mdataina 	: std_logic_vector(D*8 downto 0) ;
signal	mdatainb 	: std_logic_vector(D*4 downto 0) ;
signal	tx_data_out 	: std_logic_vector(D-1 downto 0) ;

constant TX_SWAP_MASK 	: std_logic_vector(D-1 downto 0) := (others => '0') ;		-- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.




signal counter : std_logic_vector(2 downto 0) := "000";

begin

--datain <= x"0f";

-- clock generator architecture

gclk <= gclk_int ;



bufio2_inst : BUFIO2 generic map(
      	DIVIDE			=> 1,              		-- The DIVCLK divider divide-by value; default 1
      	I_INVERT		=> FALSE,               
      	DIVIDE_BYPASS		=> TRUE,               		
      	USE_DOUBLER		=> FALSE)               	
port map (                                                  
      	I			=> clk_50mhz,  			-- Input source clock 0 degrees
      	IOCLK			=> open,	        	-- Output Clock for IO
      	DIVCLK			=> clkintb,                	-- Output Divided Clock
      	SERDESSTROBE		=> open) ;           		-- Output SERDES strobe (Clock Enable)
      	
tx_pll_adv_inst : PLL_ADV generic map(
      	BANDWIDTH		=> "OPTIMIZED",  		-- "high", "low" or "optimized"
      	CLKFBOUT_MULT		=> PLLX,       			-- multiplication factor for all output clocks
      	CLKFBOUT_PHASE		=> 0.0,     			-- phase shift (degrees) of all output clocks
      	CLKIN1_PERIOD		=> CLKIN_PERIOD,  		-- clock period (ns) of input clock on clkin1
      	CLKIN2_PERIOD		=> CLKIN_PERIOD,  		-- clock period (ns) of input clock on clkin2
      	CLKOUT0_DIVIDE		=> 1,       			-- division factor for clkout0 (1 to 128)
      	CLKOUT0_DUTY_CYCLE	=> 0.5, 			-- duty cycle for clkout0 (0.01 to 0.99)
      	CLKOUT0_PHASE		=> 0.0, 			-- phase shift (degrees) for clkout0 (0.0 to 360.0)
      	CLKOUT1_DIVIDE		=> 1,   			-- division factor for clkout1 (1 to 128)
      	CLKOUT1_DUTY_CYCLE	=> 0.5, 			-- duty cycle for clkout1 (0.01 to 0.99)
      	CLKOUT1_PHASE		=> 0.0, 			-- phase shift (degrees) for clkout1 (0.0 to 360.0)
      	CLKOUT2_DIVIDE		=> S,   			-- division factor for clkout2 (1 to 128)
      	CLKOUT2_DUTY_CYCLE	=> 0.5, 			-- duty cycle for clkout2 (0.01 to 0.99)
      	CLKOUT2_PHASE		=> 0.0, 			-- phase shift (degrees) for clkout2 (0.0 to 360.0)
      	CLKOUT3_DIVIDE		=> S,   			-- division factor for clkout3 (1 to 128)
      	CLKOUT3_DUTY_CYCLE	=> 0.5, 			-- duty cycle for clkout3 (0.01 to 0.99)
      	CLKOUT3_PHASE		=> 0.0, 			-- phase shift (degrees) for clkout3 (0.0 to 360.0)
      	CLKOUT4_DIVIDE		=> S,   			-- division factor for clkout4 (1 to 128)
      	CLKOUT4_DUTY_CYCLE	=> 0.5, 			-- duty cycle for clkout4 (0.01 to 0.99)
      	CLKOUT4_PHASE		=> 0.0,      			-- phase shift (degrees) for clkout4 (0.0 to 360.0)
      	CLKOUT5_DIVIDE		=> S,       			-- division factor for clkout5 (1 to 128)
      	CLKOUT5_DUTY_CYCLE	=> 0.5, 			-- duty cycle for clkout5 (0.01 to 0.99)
      	CLKOUT5_PHASE		=> 0.0,      			-- phase shift (degrees) for clkout5 (0.0 to 360.0)
      	COMPENSATION		=> "INTERNAL",			-- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
      	DIVCLK_DIVIDE		=> PLLD,        		-- division factor for all clocks (1 to 52)
      	REF_JITTER		=> 0.100)       		-- input reference jitter (0.000 to 0.999 ui%)
port map (
      	CLKFBDCM		=> open,              		-- output feedback signal used when pll feeds a dcm
      	CLKFBOUT		=> dummy,              		-- general output feedback signal
      	CLKOUT0			=> pllout_xs,      		-- x7 clock for transmitter
      	CLKOUT1			=> open,      			--
      	CLKOUT2			=> pllout_x1,              	-- x1 clock for BUFG
      	CLKOUT3			=> open,	              	-- x2 clock for BUFG
      	CLKOUT4			=> open,              		-- one of six general clock output signals
      	CLKOUT5			=> open,              		-- one of six general clock output signals
      	CLKOUTDCM0		=> open,            		-- one of six clock outputs to connect to the dcm
      	CLKOUTDCM1		=> open,            		-- one of six clock outputs to connect to the dcm
      	CLKOUTDCM2		=> open,            		-- one of six clock outputs to connect to the dcm
      	CLKOUTDCM3		=> open,            		-- one of six clock outputs to connect to the dcm
      	CLKOUTDCM4		=> open,            		-- one of six clock outputs to connect to the dcm
      	CLKOUTDCM5		=> open,            		-- one of six clock outputs to connect to the dcm
      	DO			=> open,                	-- dynamic reconfig data output (16-bits)
      	DRDY			=> open,                	-- dynamic reconfig ready output
      	LOCKED			=> pll_lckd,        		-- active high pll lock signal
      	CLKFBIN			=> dummy,			-- clock feedback input
      	CLKIN1			=> clkintb,	     		-- primary clock input
      	CLKIN2			=> '0', 	    		-- secondary clock input
      	CLKINSEL		=> '1',             		-- selects '1' = clkin1, '0' = clkin2
      	DADDR			=> "00000",            		-- dynamic reconfig address input (5-bits)
      	DCLK			=> '0',               		-- dynamic reconfig clock input
      	DEN			=> '0',                		-- dynamic reconfig enable input
      	DI			=> "0000000000000000", 		-- dynamic reconfig data input (16-bits)
      	DWE			=> '0',                		-- dynamic reconfig write enable input
      	RST			=> reset,               	-- asynchronous pll reset
      	REL			=> '0') ;               	-- used to force the state of the PFD outputs (test only)

bufg_tx_x1 : BUFG port map (I => pllout_x1, O => gclk_int ) ;

tx_bufpll_inst : BUFPLL generic map(
      	DIVIDE			=> S)              		-- PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
port map (
      	PLLIN			=> pllout_xs,        		-- PLL Clock input
      	GCLK			=> gclk_int,	 		-- Global Clock input
      	LOCKED			=> pll_lckd,             	-- Clock0 locked input
      	IOCLK			=> ioclk,	 		-- Output PLL Clock
      	LOCK			=> buf_pll_lckd,          	-- BUFPLL Clock and strobe locked
      	SERDESSTROBE		=> serdesstrobe) ; 		-- Output SERDES strobe

bufpll_lckd <= buf_pll_lckd and pll_lckd ;


buffers : bufg port map
(
O => clk,
I => ioclk
);






-- Serializer architecture



loop0 : for i in 0 to (D - 1) generate

io_clk_out : obufds port map (
	O    			=> dataout_p(i),
	OB       		=> dataout_n(i),
	I         		=> tx_data_out(i));

loop1 : if (S > 4) generate -- Two oserdes are needed

loop2 : for j in 0 to (S - 1) generate

-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic

mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;

oserdes_m : OSERDES2 generic map (
	DATA_WIDTH     		=> S, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR", 		-- <SDR>, DDR
	SERDES_MODE    		=> "MASTER", 		-- <DEFAULT>, MASTER, SLAVE
	OUTPUT_MODE 		=> "DIFFERENTIAL")
port map (
	OQ       		=> tx_data_out(i),
	OCE     		=> '1',
	CLK0    		=> ioclk,
	CLK1    		=> '0',
	IOCE    		=> serdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> mdataina((8*i)+7),
	D3  			=> mdataina((8*i)+6),
	D2  			=> mdataina((8*i)+5),
	D1  			=> mdataina((8*i)+4),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3 			=> '0',
	T4 			=> '0',
	TRAIN    		=> '0',
	TCE	   		=> '1',
	SHIFTIN1 		=> '1',			-- Dummy input in Master
	SHIFTIN2 		=> '1',			-- Dummy input in Master
	SHIFTIN3 		=> cascade_do(i),	-- Cascade output D data from slave
	SHIFTIN4 		=> cascade_to(i),	-- Cascade output T data from slave
	SHIFTOUT1 		=> cascade_di(i),	-- Cascade input D data to slave
	SHIFTOUT2 		=> cascade_ti(i),	-- Cascade input T data to slave
	SHIFTOUT3 		=> open,		-- Dummy output in Master
	SHIFTOUT4 		=> open) ;		-- Dummy output in Master

oserdes_s : OSERDES2 generic map(
	DATA_WIDTH     		=> S, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR", 		-- <SDR>, DDR
	SERDES_MODE    		=> "SLAVE", 		-- <DEFAULT>, MASTER, SLAVE
	OUTPUT_MODE 		=> "DIFFERENTIAL")
port map (
	OQ       		=> open,
	OCE     		=> '1',
	CLK0    		=> ioclk,
	CLK1    		=> '0',
	IOCE    		=> serdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> mdataina((8*i)+3),
	D3  			=> mdataina((8*i)+2),
	D2  			=> mdataina((8*i)+1),
	D1  			=> mdataina((8*i)+0),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3  			=> '0',
	T4  			=> '0',
	TRAIN 			=> '0',
	TCE	 		=> '1',
	SHIFTIN1 		=> cascade_di(i),	-- Cascade input D from Master
	SHIFTIN2 		=> cascade_ti(i),	-- Cascade input T from Master
	SHIFTIN3 		=> '1',			-- Dummy input in Slave
	SHIFTIN4 		=> '1',			-- Dummy input in Slave
	SHIFTOUT1 		=> open,		-- Dummy output in Slave
	SHIFTOUT2 		=> open,		-- Dummy output in Slave
	SHIFTOUT3 		=> cascade_do(i),   	-- Cascade output D data to Master
	SHIFTOUT4 		=> cascade_to(i)) ; 	-- Cascade output T data to Master

end generate ;

loop3 : if (S < 5) generate -- Only one oserdes needed

loop4 : for j in 0 to (S - 1) generate

-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic

mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;

oserdes_m : OSERDES2 generic map (
	DATA_WIDTH     		=> S, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR") 		-- <SDR>, DDR
--	SERDES_MODE    		=> "MASTER", 		-- <DEFAULT>, MASTER, SLAVE
--	OUTPUT_MODE 		=> "DIFFERENTIAL")
port map (
	OQ       		=> tx_data_out(i),
	OCE     		=> '1',
	CLK0    		=> ioclk,
	CLK1    		=> '0',
	IOCE    		=> serdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> mdatainb((4*i)+3),
	D3  			=> mdatainb((4*i)+2),
	D2  			=> mdatainb((4*i)+1),
	D1  			=> mdatainb((4*i)+0),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3 			=> '0',
	T4 			=> '0',
	TRAIN    		=> '0',
	TCE	   		=> '1',
	SHIFTIN1 		=> '1',			-- No cascades needed
	SHIFTIN2 		=> '1',			-- No cascades needed
	SHIFTIN3 		=> '1',			-- No cascades needed
	SHIFTIN4 		=> '1',			-- No cascades needed
	SHIFTOUT1 		=> open,		-- No cascades needed
	SHIFTOUT2 		=> open,		-- No cascades needed
	SHIFTOUT3 		=> open,		-- No cascades needed
	SHIFTOUT4 		=> open) ;		-- No cascades needed

end generate ;
end generate ;


Pout <= dataout_p(0);
Nout <= dataout_n(0);



                           --   every 8 clock cycles of the gigaclk ,a new payload pushed as an input to the serializer
	

 process ( ioclk) 
	
	  
	 
		begin
			
if (Rising_Edge(ioclk) ) then
      
 if (counter = "111") then  
											
									              counter <= "111";
									datain <= x"0f" ;
														 
else
									datain <= x"00" ;					
								 
						 
end if;
						 
 if (counter < "111" ) then 
						                   counter <= counter + "001";
 end if;                 
			
			end if;
      
end process;
  







end Behavioral;

 


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Teacher eteam00
Teacher
7,056 Views
Registered: ‎07-21-2009

Re: unrouted Signal

If you read the following three sections of the docs, you will understand your problem quite clearly:

 

  • UG382 v1.6, page 12, Clock Resources.  This describes the various clock buffers and what sections of the FPGA these buffers can drive.
  • DS162 Table 47, BUFGMUX Fmax spec.
  • DS162, Table 51, FOUTmax spec for BUFGMUX and for BUFPLL.

 

Summary:

 

1GHz clock cannot be distributed for use in the general purpose FPGA fabric.  BUFG (or BUFGMUX) won't go that fast.  BUFPLL will go that fast, but the IOCLK output of the BUFPLL is limited to logic in the IO region.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer anassamir
Observer
7,052 Views
Registered: ‎04-19-2011

Re: unrouted Signal

Hi Bob,

 

I guess i got your point,from what i understood that what im doing is trying to connect the output of the BUFPLL "ioclk" to the general FPGA fabric logic and this cant be done since buffers in the FPGA genral purpose logic cannot go that fast and i could only use this output in the IO region..........does this mean if i want this to work i should create the giga serializer and its PLL (for producing the high speed clock) from scratch and not using the dedicated harware in the IO region?.....

one more thing,do you know the maximum speed i could reach using  the same desgn im using(just changing the PLLX multiplying value to 8 and thus the output of the BUFPLL = 400MHz)......maximum speed of BUFMUX,since i read in the table 51 DS162 that its 400MHZ and yet i decreased the speed to that speed but still i got the same problem...unrouted signal....

 

 

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Observer anassamir
Observer
7,051 Views
Registered: ‎04-19-2011

Re: unrouted Signal

i know my questions are stupid....but its really hard for me getting close to the hardware level.....

thanks in advance bob,

Anas
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Teacher eteam00
Teacher
7,045 Views
Registered: ‎07-21-2009

Re: unrouted Signal

what im doing is trying to connect the output of the BUFPLL "ioclk" to the general FPGA fabric logic and this cant be done since buffers in the FPGA genral purpose logic cannot go that fast and i could only use this output in the IO region.

 

Absolutely spot on correct.

 

does this mean if i want this to work i should create the giga serializer and its PLL (for producing the high speed clock) from scratch and not using the dedicated harware in the IO region?

 

I'm not sure what your design requirements are, and I don't have the time and energy to reverse engineer your VHDL source code.  Having said that, the ISERDES and OSERDES logic isn't the problem.  They will run at 1GHz bit rates (in -3 speed grade devices).  The 1GHz IOCLK generated by PLL and distributed by BUFPLL is also fine.

 

It's the miscellaneous logic, residing in the FPGA fabric, which cannot run at 1GHz clock frequency, which is the immediate problem.  This is the portion of your design which needs to be re-considered.

 

i know my questions are stupid....but its really hard for me getting close to the hardware level.

 

Your questions are not stupid.  Don't be afraid to ask questions.  We don't charge extra for newbie questions.  The intricacies and details of clock buffering and interconnect resources on the Spartan-6 family devices are far from simple, and I have had trouble with details of this subject also.

 

Unfortunately, for your application, you have no alternative to "getting close to the hardware level".  If this is your first FPGA design effort, you have chosen a design target which is neither simple nor forgiving for your first project.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Observer anassamir
Observer
7,036 Views
Registered: ‎04-19-2011

Re: unrouted Signal

hi Bob,

Thanks alot for the boost up......i just read everything about the PLL outputs and i found out that i could use "gclk" which is 1ghz divide 8 = 125Mhz   and this is the clock i need for my logic....i tried using it,i faced this error during the MAPPING stage


 ERROR:Place:1136 - This design contains a global buffer instance, <bufg_tx_x1>,   driving the net, <gclk_int>, that is driving the following (first 30)   non-clock source pins.   < PIN: loop0[0].loop1.oserdes_s.D2; >   < PIN: loop0[0].loop1.oserdes_s.D1; >   < PIN: loop0[0].loop1.oserdes_s.D4; >   < PIN: loop0[0].loop1.oserdes_s.D3; >   This is not a recommended design practice in Spartan-6 due to limitations in   the global routing that may cause excessive delay, skew or unroutable   situations.  It is recommended to only use a BUFG resource to drive clock   loads. If you wish to override this recommendation, you may use the   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote   this message to a WARNING and allow your design to continue.   < PIN "bufg_tx_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; >ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

 

 

by the way i changed the code inside the process to simpler one,since the trigger now is a slower clock which is what i exactly need ,so no need for counters to slow down the clock:

 process (gclk) 
	
	  
	 
		begin
			if (Rising_Edge(gclk) ) then
                 
											
			datain <= x"0f" ;
			
			
			else 
			
			
			datain  <= x"00";
			
			end if;

  end process;
  

 

this process controls the input to the serializer depending on the gclk trigger.......as i said the clock is 125Mhz...so i guess FPGA general logic can handle it.......


Thanks alot in advance bob as usual you have been very helpful ,

Anas 

 


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Teacher eteam00
Teacher
7,020 Views
Registered: ‎07-21-2009

Re: unrouted Signal

Your design matches very closely to UG382 Figure 1-16.

 

The warning message is provoked because you are using your global clock 'gclk' as an input to either combinatorial logic or non-clock input to register(s).  You should not be doing this.  In the code snippet you posted, you are using 'gclk' as an async SET/RESET (or perhaps a MUX select) rather than a clock, and this is why the warning message is returned.

 

process (gclk)
  begin
    if (Rising_Edge(gclk) ) then
datain <= x"0f" ; else datain <= x"00"; end if; end process;

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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