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Visitor
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Registered: ‎01-16-2015

what is vcco25?

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hello, i have made a design for the spartan6 xc6slx9 which is placed on a mojo v3 development board. now i want to make a power analysis with the xpower anaylizer. to make the report more accurate i need to know the value for Vccint,Vccaux and Vcco25. in the schematic and the datasheet i have already found out the values for Vccint and vccaux, but there is nothing in the schematic or datasheet on vcco25.

 

on the schematic are several vcco pins driven by 3.3v but the allowed voltage in xpa is 2.25V to 2.75

 

can anyone help me?

 

 

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gszakacs
Professor
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Registered: ‎08-14-2007

LVCMOS outputs always swing to the power rails.  So regardless of the setting, LVCMS25, or LVCMOS33, the actual voltage swing is determined by Vcco.  On your board, that means they will swing from ground to +3.3V.

 

That is not the whole story, though.  The output buffers have a number of drive strength settings.  The standard setting is 12 mA if I remember correctly.  However the actual output buffers' drive strength depends on Vcco.  This means that the internal connections to generate 12 mA drive strength at 3.3V will be different from the settings to generate 12 mA drive strength at 2.5V.  If you tell the tools that you want LVCMOS25, they assume that Vcco will be 2.5V.  If you then apply 3.3V to Vcco, the actual drive strength will not match the settings.  Generally the same configuration will produce a higher drive strength at a higher Vcco voltage.  In addition, the clock to output delay will be a bit different from the reported values.  The input voltage threshold doesn't always depend on Vcco, though.  Some IO standards use Vccaux as a reference, but this depends on the FPGA family you use.  This means that you could have a lower input voltage threshold (lower Vih min) if you specify LVCMOS25 than if you specify LVCMOS33 even with a 3.3V Vcco supply.  You need to check the Select IO user guide for your FPGA family.  There are tables of Vcco requirements for each standard for inputs and outputs.  In Spartan 6 you also have a choice of Vccaux voltage.  Again you need to tell the tools how this is actually hooked up on the board.  Giving the tools the wrong information can result in the wrong input threshold levels in some cases.  If you see that there is no specific Vcco requirement for inputs then the threshold will not be dependent on Vcco.  So while you can still end up with a working design under some cases, it is not a good idea to power the Vcco from a voltage that doesn't match the requirements for the IO standard you selected.

-- Gabor

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umamahe
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

VCCO2.5 in XPE  indicates VCCO at 2.5V voltage level.

 

Are you refering any Xilinx board (SP601/Sp605) schematic?

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gszakacs
Professor
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Registered: ‎08-14-2007

There is an issue with your design:  It doesn match the board.

 

If you have not set the IOSTANDARD for some IO pin, it will default to LVCMOS25.  This implies that you need an IO bank powered at 2.5V  If you need a 2.5V IO standard, then your board will not work for you.  If you want your IO to actually be 3.3V like LVCMOS33, then you need to add the IOSTANDARD to your constraints.  If you tell the tools that you want a 2.5V IO standard and then run it on a bank powered with 3.3V, it may still work but it won't work as expected.  For example 2.5V LVCMOS will actually run like 3.3V LVCMOS when powered by 3.3V - outputs will swing from ground to 3.3V, not 2.5V.  They will also have higher drive than you specified and use more power.

-- Gabor
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Visitor
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Registered: ‎01-16-2015

oh thank you gszakacs,

you helped me a lot. you were right, my design didnt match the schematic. now i  added the IOSTANDARD constraint as seen below

 

NET "CLK" TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD "CLK" 1000 ns HIGH 50%;


# PlanAhead Generated physical constraints
NET "CLK" LOC = P56 | IOSTANDARD = LVTTL;
NET "Input<0>" LOC = P2 | IOSTANDARD = LVTTL;
NET "Input<1>" LOC = P5 | IOSTANDARD = LVTTL;
NET "Input<2>" LOC = P6 | IOSTANDARD = LVTTL;
NET "Input<3>" LOC = P7 | IOSTANDARD = LVTTL;
NET "Input<4>" LOC = P8 | IOSTANDARD = LVTTL;
NET "Input<5>" LOC = P9 | IOSTANDARD = LVTTL;
NET "Input<6>" LOC = P10 | IOSTANDARD = LVTTL;
NET "Input<7>" LOC = P11 | IOSTANDARD = LVTTL;
NET "Input<8>" LOC = P12 | IOSTANDARD = LVTTL;
NET "Input<9>" LOC = P14 | IOSTANDARD = LVTTL;
NET "Input<10>" LOC = P15 | IOSTANDARD = LVTTL;
NET "Input<11>" LOC = P16 | IOSTANDARD = LVTTL;
NET "Input<12>" LOC = P17 | IOSTANDARD = LVTTL;
NET "Input<13>" LOC = P21 | IOSTANDARD = LVTTL;
NET "Input<14>" LOC = P22 | IOSTANDARD = LVTTL;
NET "Input<15>" LOC = P23 | IOSTANDARD = LVTTL;

NET "Output<0>" LOC = P111 | IOSTANDARD = LVTTL;
NET "Output<1>" LOC = P112 | IOSTANDARD = LVTTL;
NET "Output<2>" LOC = P114 | IOSTANDARD = LVTTL;
NET "Output<3>" LOC = P115 | IOSTANDARD = LVTTL;
NET "Output<4>" LOC = P116 | IOSTANDARD = LVTTL;
NET "Output<5>" LOC = P117 | IOSTANDARD = LVTTL;
NET "Output<6>" LOC = P118 | IOSTANDARD = LVTTL;
NET "Output<7>" LOC = P119 | IOSTANDARD = LVTTL;
NET "Output<8>" LOC = P120 | IOSTANDARD = LVTTL;
NET "Output<9>" LOC = P121 | IOSTANDARD = LVTTL;
NET "Output<10>" LOC = P123 | IOSTANDARD = LVTTL;
NET "Output<11>" LOC = P124 | IOSTANDARD = LVTTL;
NET "Output<12>" LOC = P126 | IOSTANDARD = LVTTL;
NET "Output<13>" LOC = P127 | IOSTANDARD = LVTTL;
NET "Output<14>" LOC = P131 | IOSTANDARD = LVTTL;
NET "Output<15>" LOC = P132 | IOSTANDARD = LVTTL;

 

 

now the xpa changed vcco25 to vcco33.  But can you explain it one more time for me? if i set the IOSTANDARD to 2.5V and my vcco will be powered with 3.3V,  will my pins actually swing from Ground to 3.3V ore from Ground to 2.5v?

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gszakacs
Professor
Professor
18,526 Views
Registered: ‎08-14-2007

LVCMOS outputs always swing to the power rails.  So regardless of the setting, LVCMS25, or LVCMOS33, the actual voltage swing is determined by Vcco.  On your board, that means they will swing from ground to +3.3V.

 

That is not the whole story, though.  The output buffers have a number of drive strength settings.  The standard setting is 12 mA if I remember correctly.  However the actual output buffers' drive strength depends on Vcco.  This means that the internal connections to generate 12 mA drive strength at 3.3V will be different from the settings to generate 12 mA drive strength at 2.5V.  If you tell the tools that you want LVCMOS25, they assume that Vcco will be 2.5V.  If you then apply 3.3V to Vcco, the actual drive strength will not match the settings.  Generally the same configuration will produce a higher drive strength at a higher Vcco voltage.  In addition, the clock to output delay will be a bit different from the reported values.  The input voltage threshold doesn't always depend on Vcco, though.  Some IO standards use Vccaux as a reference, but this depends on the FPGA family you use.  This means that you could have a lower input voltage threshold (lower Vih min) if you specify LVCMOS25 than if you specify LVCMOS33 even with a 3.3V Vcco supply.  You need to check the Select IO user guide for your FPGA family.  There are tables of Vcco requirements for each standard for inputs and outputs.  In Spartan 6 you also have a choice of Vccaux voltage.  Again you need to tell the tools how this is actually hooked up on the board.  Giving the tools the wrong information can result in the wrong input threshold levels in some cases.  If you see that there is no specific Vcco requirement for inputs then the threshold will not be dependent on Vcco.  So while you can still end up with a working design under some cases, it is not a good idea to power the Vcco from a voltage that doesn't match the requirements for the IO standard you selected.

-- Gabor

View solution in original post

allstar
Visitor
Visitor
10,417 Views
Registered: ‎01-16-2015

Thank you very much for this good post, you almost gave me too much information at once xD. 

 

you really helped me

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