UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor rvndrlt
Visitor
6,012 Views
Registered: ‎04-03-2012

xapp495 and PLL_ADV

I'm using an Atlys board with spartan 6 to test xapp495. I'm trying to add simple ethernet communication based on another project that i have working satisfactorily. My problem is that the xap495 project uses 4 PLL_ADV's then the clock driving the ethernet portion of the design adds 1 more PLL_ADV which puts it over the resources on the board. Or so it seems based on the errors I see.  The ethernet portion uses a clock generator with a 100MHz input and outputs 125MHz at 0 degrees and another 125 at 90 degrees.  My question is - is there another way to generate this outside of a PLL_ADV? It looks like the DCM's won't work. I made a lame attempt at generating the signals off one of the existing PLL_ADV's unused outputs but got more errors so I'm hoping there's another way. Any ideas? 

0 Kudos
5 Replies
Teacher eteam00
Teacher
6,010 Views
Registered: ‎07-21-2009

Re: xapp495 and PLL_ADV

I made a lame attempt at generating the signals off one of the existing PLL_ADV's unused outputs but got more errors so I'm hoping there's another way. Any ideas?

 

This is the correct approach to take, but apparently you did it wrong.

 

You can use the ISE coregen clock wizard to figure out the correct PLL_ADV settings you need, and then you can apply these settings to the PLL_ADV you will use to generate the ethernet clocks.

 

Post or describe the error messages your first attempt provoked, if you want specific corrective guidance.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor rvndrlt
Visitor
5,996 Views
Registered: ‎04-03-2012

Re: xapp495 and PLL_ADV

thanks. i'll keep trying and post if i can't figure it out. i appreciate the nudge in the right direction.

0 Kudos
Visitor rvndrlt
Visitor
5,982 Views
Registered: ‎04-03-2012

Re: xapp495 and PLL_ADV

I worked through a few errors but got stuck on these:

 

ERROR:Place - ConstraintResolved NO placeable site for tx0_ioclk_buf
ERROR:Place:1238 - Component "PLL_OSERDES_0/PLL_ADV" does not have a feasible
site.
There are 12 potential locations for the component:
ERROR:Place:1201 - Component <PLL_OSERDES_0/PLL_ADV> of type PLL is not
placeable because it has locked loads placed in regions: CLOCKREGION_X1Y4
CLOCKREGION_X1Y4.
There is a restriction that the clock loads of a PLL must be in a
horizontally adjacent clock region to the PLL. It is recommended that a BUFG
be used for this clock signal so that the clock loads can be placed anywhere
on the device. If the clock driver or clock loads are locked or area grouped,
please ensure that they are constrained to horizontally adjacent clock
regions.

 

I believe the errors refer to this part of the design:

 

PLL_BASE # (
    .CLKIN_PERIOD(10),
    .CLKFBOUT_MULT(10), //set VCO to 10x of CLKIN
    .CLKOUT0_DIVIDE(1),
    .CLKOUT1_DIVIDE(10),
    .CLKOUT2_DIVIDE(5),
    .CLKOUT3_DIVIDE(8), 
    .CLKOUT4_DIVIDE(8), 
    .CLKOUT4_PHASE(90.000),
    .COMPENSATION("SOURCE_SYNCHRONOUS")
  ) PLL_OSERDES_0 (
    .CLKFBOUT(tx0_clkfbout),
    .CLKOUT0(tx0_pllclk0),
    .CLKOUT1(),
    .CLKOUT2(tx0_pllclk2),
    .CLKOUT3(clk_125),
    .CLKOUT4(clk_125_GTX_CLK),
    .CLKOUT5(),
    .LOCKED(tx0_plllckd),
    .CLKFBIN(tx0_clkfbin),
    .CLKIN(tx0_pclk),
    .RST(tx0_pll_reset)
  );

  BUFGMUX tx0_bufg_pclk (.S(select[0]), .I1(rx1_pllclk1), .I0(rx0_pllclk1), .O(tx0_pclk));

  //
  // This BUFG is needed in order to deskew between PLL clkin and clkout
  // So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
  //
  BUFG tx0_clkfb_buf (.I(tx0_clkfbout), .O(tx0_clkfbin));

The error states " It is recommended that a BUFG be used for this clock signal ". The CLKIN and CLKFBIN are routed through a BUFG - I don't know if that's what the error is refering to, it appears a BUFG is already being used.

 

I saw another post with the same error but I didn't understand the answer - "We have exchanged BUFG against a logic block.". Would this help in my situation? If so what does this mean and how do I accomplish it?

0 Kudos
Teacher eteam00
Teacher
5,977 Views
Registered: ‎07-21-2009

Re: xapp495 and PLL_ADV

You seem to have a big stinking steaming pile of mess on your hands.

 

The error message references a PLL_ADV, not a PLL_BASE.  Did you notice that?

 

It seems that you have made major additions and changes to a (hopefully working) code base, and you have no idea where in this pile of code your problems may be found.  This is a classic "find the needles in the big haystack" problem.

The error message references a PLL_ADV, not a PLL_BASE.  Did you notice that?

 

This bit of the code snippet you posted does not make sense.  Not only is the feedback clock incorrect, the comments refer to signal (clocks) which are not named or connected in the code you posted.  Comments referring to missing signals are not very useful.

 

BUFGMUX tx0_bufg_pclk (.S(select[0]), .I1(rx1_pllclk1), .I0(rx0_pllclk1), .O(tx0_pclk));

// This BUFG is needed in order to deskew between PLL clkin and clkout
// So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
BUFG tx0_clkfb_buf (.I(tx0_clkfbout), .O(tx0_clkfbin));

 

Here is a suggested approach for hanging onto your sanity:

 

  • Revert back to the original Atlys reference design, and verify that you can build (synthesise) this reference design without errors.  If you are getting errors, then you need to clean them up before proceeding further.
  • Add or change one thing at a time, and verify that your changes and additions will synthesise as expected before proceeding on to the next change or addition.  If you do not understand an immediate problem, this approach will allow you to describe with reasonable accuracy the changes you made since the last "clean" synthesis.
  • Continue until all the desired changes and additions have been made.

Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor rvndrlt
Visitor
5,964 Views
Registered: ‎04-03-2012

Re: xapp495 and PLL_ADV

Thanks for your reply.

 

Yes, I saw that the synthesis tool replaced the PLL_BASE with a PLL_ADV. I figured explicitly replacing the PLL_BASE wouldn't help anything since the PLL_ADV seems to be an expanded PLL_BASE. But that's why I posted only that particular piece of code, I believe the issue is there.

 

Looking back at the post you're absolutely right, I should have shown a more organized snippet. I was pretty frustrated at that point.

 

The approach I took was I started with two working designs and attempted to just combine them all at once.  Is this incorrect? Each time I tried to build it, I got errors, fixed them, then got new ones and repeated. I wouldn't say either design has changed too significantly at this point, but I get the feeling I started with the wrong approach.

 

0 Kudos