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Clock Inverting

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Visitor
Posts: 16
Registered: ‎08-28-2017
Accepted Solution

Clock Inverting

I just took over an old design, which had a clock architecture like the following code. I don't have much information about why they design it this way. the sysclk is the main system clock used all over the Spartan 3 FPGA, my question is after the ISE synthesizer, will the sysclk be put on a global clock trace? if not where should I put this inverter? what is the difference between IBUFG and BUFG, I notice in the design xout was not used by any logic. if I use the xout to drive the system clock what is the difference between the noninv_sysclk other than phase?

 

appreciate your help.

 

David Sun

 

dcm1 u3(
.RST_IN(sys_res),
.LOCKED_OUT(),
.CLKIN_IN(sysclk_in),
.CLKDV_OUT(clk_adc), // adc clock

.CLKIN_IBUFG_OUT(noninv_sysclk), // reversed for up interface timing
.CLK0_OUT(xout) // was sysclk, CLK0_OUT doesn't have an IBUFG!
);

assign sysclk = !noninv_sysclk;

 

 


Accepted Solutions
Historian
Posts: 4,559
Registered: ‎01-23-2009

Re: Clock Inverting

what is the difference between IBUFG and BUFG

 

These are NOT at all the same thing. Take a look at this post on the difference between a BUFG and an IBUFG.

 

will the sysclk be put on a global clock trace?

 

The answer to this is complicated. First, be aware that this is the instantiation of a clock module generated by the clocking wizard (presumably) - it is not the direct instantiation of hte DCM.

 

The clocking module is configurable, and hence it

  - may or may not have an IBUFG bringing the clock in

  - may have one of several different types of DCM feedback mechanisms implemented

  - may or may not have clock buffers on the output clocks and, depending on architecture, may have one of several different types of clock buffers (not in a Spartan-3)

 

In this case, presumably the module has an IBUFG to bring the clock into the FPGA, connected to the CLKIN of the DCM. However, in addition, the output of the IBUFG is brought out of the clock module directly - not through any clock buffer. What happens to it from here depends on what is done after this instantiation.

 

Assuming this goes to a BUFG (either instantiated or inferred), then the inversion is probably not a problem. The clock input to each slice in the FPGA has an optional inverter, so if the clock on the clock network is the "wrong" polarity, the slices can invert it. The only concern I have is that, as coded, the inversion would end up before the BUFG - the tools would have to push it to after.

 

Of course, the better way is to use the CLK180 output of the DCM...

 

Avrum

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All Replies
Xilinx Employee
Posts: 9,292
Registered: ‎02-27-2008

Re: Clock Inverting

The code snippet in not inverted clock.

 

The DCM, MMCM, or PLL inverted clock source is CLK_180.  CLK0 is non-inverted clock source.

 

Never trust the comments in old code.  Comments are not used for synthesis, so they might as well be gibberish for all they are worth.

 

You did not mention what new device you are targeting.

Austin Lesea
Principal Engineer
Xilinx San Jose
Historian
Posts: 4,559
Registered: ‎01-23-2009

Re: Clock Inverting

what is the difference between IBUFG and BUFG

 

These are NOT at all the same thing. Take a look at this post on the difference between a BUFG and an IBUFG.

 

will the sysclk be put on a global clock trace?

 

The answer to this is complicated. First, be aware that this is the instantiation of a clock module generated by the clocking wizard (presumably) - it is not the direct instantiation of hte DCM.

 

The clocking module is configurable, and hence it

  - may or may not have an IBUFG bringing the clock in

  - may have one of several different types of DCM feedback mechanisms implemented

  - may or may not have clock buffers on the output clocks and, depending on architecture, may have one of several different types of clock buffers (not in a Spartan-3)

 

In this case, presumably the module has an IBUFG to bring the clock into the FPGA, connected to the CLKIN of the DCM. However, in addition, the output of the IBUFG is brought out of the clock module directly - not through any clock buffer. What happens to it from here depends on what is done after this instantiation.

 

Assuming this goes to a BUFG (either instantiated or inferred), then the inversion is probably not a problem. The clock input to each slice in the FPGA has an optional inverter, so if the clock on the clock network is the "wrong" polarity, the slices can invert it. The only concern I have is that, as coded, the inversion would end up before the BUFG - the tools would have to push it to after.

 

Of course, the better way is to use the CLK180 output of the DCM...

 

Avrum

Visitor
Posts: 16
Registered: ‎08-28-2017

Re: Clock Inverting

I was surprised by the speed of the response of this forum. I am quite sure the answer is just what I need. but I need more time to digest it. 

Thank you so much. will ask more questions soon. 

 

David Sun