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Downsampling (decimating) or using two clock signals?

Posts: 15
Registered: ‎11-12-2010

Downsampling (decimating) or using two clock signals?


Finally I am able to get data from AD6645 evaluation board and feed AD9764 evaluation board using Spartan 3 AN FPGA. Here are the pictures of the experimental system, the results in Chipscope and oscilloscope for 1 MHz input sine wave (DAC output, since the configuration consists of taking analog signal to  AD6645 then to FPGA then to AD9764).

Experimental setup:


Oscilloscope view of DAC output:


Chipscope analysis:

In a few days instead of cables i will use circuit board to connect all the boards together.


I have a question.

AD6645 EVM is shipped with onboard 105 MHz clock oscillator which has the following features a load capacitance of 50 pF, +-100ppm, 10ms of max setup time. I need to sample the incoming ADC data with 16 MHz because of the FPGA code. However AD6645 has a minimum sampling rate of 30MHz. Instead of changing my FPGA code i think about three possible solutions.

The first of them is downsampling (decimating) the ADC data but this consumes FPGA design area and ADC output synchronization is hard.

In the second one i try to use two DCM's to create ADC sampling clock of a multiple of 16 MHz and a 16 MHz clock for AD9764 and signal processing in the FPGA code.

As a third method i want to put another clock oscillator on the AD6645 ADC EVM module instead of the shipped one (AC53R, 105 MHz) and dividing this clock by the required value to obtain 16 MHz clock which is synchronised with the ADC clock.


What is your suggestion about this subject? What are the specifications needed for the ADC clock oscillator? Will there be a change in the load capacitance, setup time specifications if I use for example a 64 MHz clock instead of the 105 MHz clock given? Is there any clock oscillator suggestions for the ADC sampling at 16x MHz? (one can be like the one in AD6644 evm datasheet : MXO45LV). Because when I used some oscillators I was not able to get data using Chipscope  because it says the clock signal is too slow.


Thank you very much,


Posts: 1,119
Registered: ‎10-05-2010

Re: Downsampling (decimating) or using two clock signals?

You might have more luck asking questions about the Analog Devices part on their forum!


ChipScope Pro doesn't actually mind if a clock is slow. Usually it will give you that error if there is no clock at all. Make sure you verify that the different oscillator is actually working. If the clock is being sent to the FPGA, you could forward it out to another pin and look at it on your oscilloscope to make sure it's actually making it into there.


By the way, I would be wary of signal integrity problems with your wiring arrangement.