04-21-2017 12:22 AM
With some reference to these posts -> Virtex GTP live control and Spartan 6 GTP config for which there are no subsequent follow-ups or descriptions of what happened afterwards, I would like to ask if other users have purposefully and successfully changed the GTP Transceiver Swing and Pre-Emphasis control values, what values they now use and why they did it .. ?
We have a PCIe link between the Spartan 6 and a Com Express Module that occasionally fails on the FPGA transmit signals. Protocol analysis reveals illegal characters or incorrect 8b/10b encoding. I had the idea that maybe the issue was borderline signal integrity and have looked at adjusting these values but I can find no real info about what values mean what effect in reality.
Some guidance would be appreciated.
04-23-2017 04:32 AM
Please refer below documents, I hope it helps
04-24-2017 12:20 AM
Well, yes, thank you. I have already seen and read these documents.
What I am not sure about is why or when I might need to change the values. I can fish about and experiment, of course, but I would like to have an understanding of why I would vary from the default values given in the Xilinx provided Verilog wrapper for the GTP tile.
e.g. for what possible reasons would I increase/decrease the Swing voltage from 997 mV ppd ? High speed comms links are not my area of expertise and I don't fully understand the physics behind the signal control.
The documents you link to simply tell me what the signals do - there's no explanation of under what circumstances one would change them. Technically it would be possible to bring the signals up to a higher level and control the swing and pre-emphasis dynamically - why would anyone do that?
04-24-2017 12:38 AM
04-24-2017 10:49 AM
I've been spending considerable amount of time bringing up PCIe links using Xilinx PCIe controllers on different HW platforms.
The way you approach the problem depends on the link speed. If PCIe is Gen1 (runs at 2.5Gbs), the link should work "as is". At Gen2 (5.0Gbs) speeds, signal integrity becomes more critical. At Gen3 (8Gbs) speeds, PCIe has built-in mechanism to adjust swing and preemphasis of Tx signal by exchanging special commands over PCIe link.
Look at LTSSM state bus inside the PCIe controller. Normal operation is LTSSM state L0 after link training. Make sure what you see is LTSSM going to Recovery state. If you have access to protocol analyzer, determine which side (upstream or downstream device) is causing Recovery.
I've seen several signal integrity problems with PCIe links at different speeds. One of the latest examples was power switching regulator modulated noise at few KHz got transferred to PCIe data lanes. It caused the link periodically go to Recovery state at Gen1 rate, and the link never trained to Gen2/Gen3. I did experiment with swing and preemphasis values, and it appeared to fix the problem. But it was a patch, not fix of the root cause. The real fix was putting a filter on power rails.
So yes, as a debug tool you can try different swing and preemphasis values to see what effect they have on the link. But the real fix probably lies elsewhere.