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Observer alexmiculescu
Observer
1,906 Views
Registered: ‎11-11-2016

Intel hex Memory_ContentFile Altium

Hello. I would be very thankful if you could help me out initialising Memory_ContentFile from the pdf attached at pag. 418.

Is there any hex editor or something like this to write my hex file in this form:

0000F
0000A
00001

A023A

.

.

.

.

.

and get my intel hex data? Thank you!

 

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1 Reply
Observer alexmiculescu
Observer
1,900 Views
Registered: ‎11-11-2016

Re: Intel hex Memory_ContentFile Altium

I also tried modeling a dual port ram using verilog but I get the following synthesis error: 

[Error] true_dpram_sclk.v(23) Altium Synthesizer net ram[7][19] is constantly driven from multiple places.

 

Code:

 

 

module true_dpram_sclk
(
    input [19:0] DINA, DINB,
    input [7:0] ADDRA, ADDRB,
    input WEA, WEB, CLKA, CLKB, reset,
    output reg [19:0] DOUTA, DOUTB
);
    // Declare the RAM variable
    reg [19:0] ram[7:0];

    // Port A
    always @ (posedge CLKA)
    begin
        if (WEA)
        begin
            ram[ADDRA] <= DINA;
            DOUTA <= DINA;
        end
        else
        begin
            DOUTA <= ram[ADDRA];
        end
    end

    // Port B
    always @ (posedge CLKB)
    begin
        if (WEB)
        begin
            ram[ADDRB] <= DINB;
            DOUTB <= DINB;
        end
        else
        begin
            DOUTB <= ram[ADDRB];
        end
    end

endmodule

What is wrong here?

 

The snippet below gets the same error:

 

https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver-true-dual-port-ram-sclk.html

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