UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie spilipchuk
Newbie
17,033 Views
Registered: ‎03-14-2014

Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Hi,

Yes so the questions is whether or not the Spartan-6 I/O inputs are 5V tolerant. Looking at the datasheet seems like they are not. Am I correct?

Thanks

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
25,231 Views
Registered: ‎01-03-2008

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

The Spartan-6 data sheet is clear that the maximum input voltage (Vin) is 4.0V, so the I/Os that you have connected to 5V are degrading and will eventually fail.

 

Connecting a Spartan-6 output buffer to the another devices input that is expecting 5V will not cause 5V to applied to the Spartan-6 device and will not cause degradation.  You will need to check the other device's data sheet to determine if the 3.3V level will be recognized as a logic 1 state.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
22 Replies
Participant cesys
Participant
17,031 Views
Registered: ‎08-02-2013

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

You are right. Do not apply 5 Volts to Spartan-6 IOs - not even for a short time. This will surely brick your FPGA.

 

-Manfred

Newbie spilipchuk
Newbie
17,025 Views
Registered: ‎03-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

I want to add that I already have a board made with Spartan-6 FPGA and some 5V signals going into it and it seems to work fine.

For example I have several 5V level inputs that first run through a 1k resistor than a buffer (74HC244M) and then into S6 FPGA.

I also have one input coming directly from AS5245 running in 5V configuration.

 

Also what about hooking up an S6 output to a 5V input. For example I have one output directly connected to ADM2485 pin-8. ADM2485 is powered by 5V (pin-4).

0 Kudos
Xilinx Employee
Xilinx Employee
25,232 Views
Registered: ‎01-03-2008

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

The Spartan-6 data sheet is clear that the maximum input voltage (Vin) is 4.0V, so the I/Os that you have connected to 5V are degrading and will eventually fail.

 

Connecting a Spartan-6 output buffer to the another devices input that is expecting 5V will not cause 5V to applied to the Spartan-6 device and will not cause degradation.  You will need to check the other device's data sheet to determine if the 3.3V level will be recognized as a logic 1 state.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Newbie spilipchuk
Newbie
17,018 Views
Registered: ‎03-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution
Thank you.The fact that the design seems to function perfectly had me doubting whether I was interpreting the datasheet correctly.
0 Kudos
Instructor
Instructor
17,016 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

74ASxx as well as other bipolar logic families like 74xx, 74ALSxx and 74Fxx all have very weak high drive once the output voltage is above about 3.5V.  This probably explains why you haven't already damaged the S6.  On the other hand 5V CMOS logic generally has significant drive at or above 4V and will damage the S6 - even with a series resistor.  Note that S6 does not have clamp diodes to Vcco like some other families and therefore your resistor will not prevent the possibility of avalanche breakdown on the S6 inputs.

-- Gabor
0 Kudos
Highlighted
16,970 Views
Registered: ‎03-17-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

 

Hi ,

       I am  Mahesh and I get trapped in one problem. I am using SP 601 SPARTAN 6 board. In that IO bank 0,1 and 2 are compatible with 2.5 V(from its datasheet) . I am going to interface it with output of of other board which is 3.3 V . So what  should I do to overcome this problem? Thanks in advanced.

Tags (1)
0 Kudos
Participant cau4kien
Participant
15,379 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

If a signal (D output of a MOSFET SI1406DH-T1-E3, which is rated at 1.8 v: Drain Source is 20V Gate Source is 5 V via a 5 ohms resistor) was connected to a Spartan 6 IO, if the MOFET failed for any reason, is there any chance that the input signal can damage the chip?

 

I noticed that the FET is very hot when testing the code (I did not design the board, just coding ...), then now the FPGA seems "be bricked". Not try to blame anyone, but honestly I am not very good in the physical electrical design, have been in coding for long time ....

 

Any lecture on this subject is appreciated.

0 Kudos
Participant cau4kien
Participant
15,373 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Ooops,

 

source was connected to GND,

Mosfet.PNG
0 Kudos
Instructor
Instructor
15,369 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Two things:

 

1) this is a very old thread and not likely to be noticed by anyone who didn't originally subscribe to it.  So you should start a new thread for your topic.

 

2) A picture is worth a thousand words.  You can attach a picture showing the FET connections in the schematic to help someone answering your question.  Also if you talk about a specific non-Xilinx part like your FET, then it is better to post a link to the device data sheet, or else at least give the relevant information like is this a P-channel or N-channel FET.

-- Gabor
0 Kudos
Teacher eteam00
Teacher
10,942 Views
Registered: ‎07-21-2009

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

You are dissipating up to 5 watts in the 4.99 ohm resistor when the nFET is turned on.  That would definitely cause some device warming (in the resistor).

 

You should consult a real hardware design engineer for help with understanding the circuit board for which you are debugging.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Participant cau4kien
Participant
10,928 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Agreed about point #1, but it related to Xilinx IO inplementation,  4v max is recommed for Spartan 6 IOs .. Implenetation : 5v connetced to the gate of this mosfet, is it possible a dammage of this fet can kill the FPGA which I now have in hand: a dead  one.

Extra information, the FPGA was working fine, during debug the SDK died, I notice it's very hot at this FET area ... it's (FET)  was unused, there is no drive to the Drain of the FET.

 

I did say the part is SI1460 DH-T1-E3 right ? and this picture taken from schematic page.

0 Kudos
Instructor
Instructor
10,924 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Your schematic doesn't show any connection to the FPGA, only to the FET.  The gate of the FET is shown connecting to signal "VD5_DUMP_SNS1" but you just said it connects to 5V.  What terminal of the FET (if any) actually connects to the FPGA?  If none, are you asking if the FET could destroy the FPGA simply by heating up the baord?

-- Gabor
0 Kudos
Participant cau4kien
Participant
10,922 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Gabor, I am not that dumb,

 

" If none, are you asking if the FET could destroy the FPGA simply by heating up the baord?"

 

The simple fact is after experiencing a very high temperature at the area surrounding the FET, which I was siiting there to debug, suddenly the SDK stopped, now I can't start FPGA in SDK any more. a replacement board is working (booting) fine ...

 

VD5_DUMP_SNS1 signal is physically connected to an FPGA IO PAD (output port), which we don't use for this application so I took that IO pin assignment out of the top level RTL design as well as ucf file.

However, the physical trace and power, as well as MOSFET, serial 4.99 ohm resistor are existing in the board.

 

K

0 Kudos
Instructor
Instructor
10,918 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

It's rather unusual for a MOSFET to blow in a way that shorts anything to the gate, but I suppose it could happen.  Was there also a pullup on the VD5_DUMP_SNS1 pin that might have left the FET on when the FPGA was not driving the pin low?  Another possibility is that the unused I/O was programmed in the bitstream to pullup.  And one more possibility is if you were using indirect SPI programming from Impact.  That turns on pullups on "unused" I/O during the programming process.  This would leave the FET on for extended periods of time and could cause heat-related failure, although it looks like the 5 ohm resistor would take the brunt of that heat, not the FET.  Yet another possibility is a higher impedance "short" caused by poor cleaning of aqueous flux.  If for example the FET's gate and drain were connected with a few K ohms due to incompletely rinsed flux, the FET could get biased into a linear region where it would heat itself up.  I've seen such shorts that did not manifest themselves right away, but became stronger due to additional moisture.

 

The only other thing I can think is that perhaps something was mechanically shorted, for example when probing with a scope and two leads of the FET were bridged by the probe tip.  I have seen many chips get blown out that way.

-- Gabor
0 Kudos
Participant cau4kien
Participant
10,916 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution
Gabor,

Your answer is very much in-line with my thinking, and for sure I don't any probe tip on my desk, I was just sitting there looking at the content of DDR2 memory of the design via SDK windows, then it was "blown" up i.e. stopped displaying memory content. I checked the board, felt extreme heat on that area. I started to look at the schematic, found the MOSFET ... I am surprised with what happened too.
For the new board, I am driving that VD5_DUMP_SNS1 (an output port) or other signals to other FETs to the logic '0' to disable the FETs. It was an innocent "stupid" mistake to leave those ports floating. I think it should be OK as I understand the logic to protect the FPGA.

K
0 Kudos
Participant cau4kien
Participant
10,865 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Gabor,

 

It happened again with the other board (even all unused MOSFET's drains were turned off by connected to GND). It happened when I downloaded new bit stream via Impact to use with ChipScope. Imppact downloaded bit stream succesffuly (at least as it reported on screen), but when I triggered with all trigger are "xxxxxx", ie just want to see the snapshot at that moment, Chipscope report: "waiting for core to be arm, slow clock or stoppped" see other post I have in Emmbedded Development Tools Section.

 

Could you please elaborate more about the statement:

 

>> And one more possibility is if you were using indirect SPI programming from Impact.  That turns on pullups on "unused" I/O during the programming process <<

 

In this board with the intention to serve 2 different applications, many I/O pins were already assigned, but in the top-level design and ucf files I have only the IO pins for the application I'm working on and removed the I/O pins of other application however the physical traces existed (due to error in ISE Place and Route for the unconneced pins) . Is it possible the issue there? 

 

I thought about to ground or pull-up all the unused pins as practical even if those IO pins were not existed in the design, but I don't think it is necessay, and ridiculous because many designs never used all available IOs, Xilinx  tools and design methodology should be able to take care all unused pins right ? Maybe it was a bad assumption ...

 

 

0 Kudos
Instructor
Instructor
10,852 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

By default, ISE will pull down unused pins.  Generally speaking it is not a good idea to leave CMOS logic inputs floating.  You can see the options for unused pins in the "configuration options" tab of the process properties for "Generate Programming File."

 

Now you'll see that there are really two problems with unused IO pins.

 

1)  Keeping the FPGA pins from floating.  Any option other than "Float" will work for this.

 

2) Keeping a valid usable logic level on other board circuitry connected to the unused IO pins.  Pullup or pulldown can often work OK for this, but it's generally better to use board level resistors if there are specific requirements for high or low levels.

 

A note on item 2:

  It's a bad idea to use the FPGA alone to guarantee that a signal is in a particular state before configuration is complete.  During the initialization period after power-up or assertion of PROGRAM_B, while INITB is still low the IOB's all float.  During the time while configuration is actively going on (after INITB rises and before DONE) the pins are either floated or pulled up depending on the HSWAPEN pin setting.  Note that so far there is no option to pull down.  After configuration is complete you can program individual pins to do whatever you want.

 

The point about indirect SPI:

 

  The process pf programming a SPI flash via JTAG actually downloads a bitstream to the FPGA whose sole purpose is to take JTAG commands and use them to communicate with the SPI flash.  This bitstream is generated at Xilinx, and you don't have access to the source code it was compiled from.  Unless you ask Xilinx specifically to have some other option for unused IO pins, this bitstream will pull up all "unused" IOB's.  I put "unused" in quotes here because it refers to pins not used by the programming core, which includes all of the FPGA pins not related to the SPI connections.  As you can see, this means that even pins you use in your design will be pulled up during this process, so you can't rely on your HSWAPEN setting to ensure that pins are floating.

-- Gabor
0 Kudos
Participant cau4kien
Participant
10,845 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Gabor,

 

Thanks for your response,

Yes, I DID set the unused iOB pins to be pulled down.

There is no way the software programming can kill the hardware, the hardware is not completely dead,: the chip still can be programmed by using both ways : Impact or SDK BOTH TOOLS REPORTED PROGRAMMING DONE SUCCESFULLY but the application can't start.

SDK said the microblaze is under arrested ... Oooops under reset, buy which ? absolutely not by programming code I wrote : I have several versions of bit stream: worked fine.

Chipscope said : waiting for core to be armed, slow clock or stopped.

 

 

At first I thought the FET design in my board may cause damage on IO pins because of the possibility of 5V short circuit ... now I already disabled all FET by grounding the input to FET, and no sign of heat problem on any components.

 

I recalled, this is the sequence of work for both boards:

    - Downloading programming file through Impact

    - Run Chipscope to debug/analyze the signals

found error, mistake .. stop Chipscope trigger, maade changes in RTL, simulate etc... go though the whole cycle to generate the programming file:

   - Downloaded programming file through Impact

   - Ran Chipscope with no trigger (just want to see the snapshot at that moment.

No response from CHipscope.

Recycled power to the target board, start SDK, download files as ususal : XMD and SDK said good,

Run debug by lauching on hardware: failed, microblaze is under reset ?????

 

It looks like my FPGA is a brick, excepted the boundary scan chain via JTAG cable. Now I'm pretty sure that if I got the new board ...  it's gonna work, but eventually this scenario will repeat ... I have no glue where to look ????

 

Ggenerate Ptoramming Bit Stream.PNG
Impact Programming.PNG
0 Kudos
Instructor
Instructor
10,839 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

Do you still have the last version of the FPGA firmware that you were able to run with the SDK?  If you can get this older version running, then there must be something in the code or the re-build that caused the problem.

 

Make sure that there are no pins in the design missing a LOC constraint.  Such pins could be re-assigned when you re-build.  You can check this in the pinout report.  In the spreadsheet view you can sort by clicking column headings to make this easier.  I usually sort by signal name to see all pins in the design above the unused pins, then scroll down to make sure all of these pins have LOC constraints.  You can also look in the place & route report for lines like:

 

IO Utilization:
  Number of bonded IOBs:                       125 out of     300   41%
    Number of LOCed IOBs:                      125 out of     125  100%
    IOB Flip Flops:                             18
    IOB Master Pads:                            10
    IOB Slave Pads:                             10
    Number of bonded IPADs:                     18
    Number of bonded OPADs:                     16

Note that LOCed IOBs should always show 100%

 

You said "There is no way the software programming can kill the hardware," which is generally true of microprocessors, but not for FPGA's.  I have burnt up parts by programming an inappropriate bit file causing IO drive contention.

-- Gabor
0 Kudos
Participant cau4kien
Participant
7,001 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

I have many versions of bit stream which were working files (lesson learned about coding: always make backup :-) ), the first thing when I had problem is used to backup file to sort out  the issues ...

I looked at the design summary reports of all "golden" versions as well as the problem version:

 -- Number of bonded IOBs  125   316  39%

 -- Number of LOCed IOBs    92     125  73%

 

I did remove all unused pins out of top-level file as well as ucf, constraint file. What does it mean ?

 

BTW, I'm getting close to sort out the problem, in the power supply circuitry the designer used LM26420 (Step Down DC DC Regulator) with output current of 2 A , while the Spartan 6 DC and Switching Document page #6 and #7 said (for my device xc6slx45fgg484) :

 I ccintQ    15 mA

 I ccoQ        3 mA

 I ccAuxQ    5 mA

 

It definitely is the  problem, unless there was a limiited current circuitry some where right ?

0 Kudos
Participant cau4kien
Participant
6,999 Views
Registered: ‎05-14-2014

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution
Over supply current may not be that bad, excepted there is a short circuit I think.
0 Kudos
Instructor
Instructor
6,995 Views
Registered: ‎08-14-2007

Re: Is Spartan-6 Inputs 5V tolerant?

Jump to solution

All those current specs with a "Q" at the end are quiescent current.  Once your design is loaded and running you will have significantly more current.

 

The only possible problem with low quiescent current is if the power supply has a minimum output current requirement.  Switching power supplies typically don't have such a requirement.

 

In any case this is bad:

 

 -- Number of LOCed IOBs    92     125  73%

 

especially if any of the 33 un-LOCed IOBs are outputs.  If you define a pin as an output, but don't ever drive it in the design, the default action is to actively drive it low.  Add to that the fact that this driven pin will be randomly assigned on each build and you have a source of problems.

-- Gabor
0 Kudos