09-05-2013 10:04 AM
I want to know whats the maximum clock frequency over which AXI system can opeate.
Detailed manual's link would be helpfull for me.
09-05-2013 10:15 AM
Any logic implemented in the FPGS device willl operated at the frequency it was constrained to operate at (timing constraint), unless the constraint is too aggressive (the circuits cannot be placed and routed to meet the goal).
So, depending on what else is present, and the device, the frequency is what it is (and different). Printing it in any manual would be a waste of time, and energy.
Only the final placed and routed design, meeting the proper timing constraints can answer the question -- so, I ask you: "what frequency is your design constrained for, and successfully meeting?"
Only you can answer.
09-07-2013 08:23 AM
That depends upon type of application.
In case of AXI-4 stream video IP thebelow link is useful. The range of Clock also specified http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf
08-03-2018 01:28 PM
So in my design I am using " AXI4-Stream Interconnect RTL (1.1)" IP core.
I am running my design at 500 Mhz.
In the timing summary, vivado shows negative slack within this ip core. Meaning the data path lies within the ipcore.
does that mean this module cannot function at 500Mhz ? or Are there any possible solutions ?
I have included a screenshot for the datapath of the negative slack.
"axis_interconnect_I2" is the instantiation name for this ipcore.