05-10-2018 02:08 AM
What is the minimum frequency advisable for CRII CPLDs. Can I give a 20/50Hz clock signal as input. Also, can I use 555 timer/opamp based oscillators for this purpose?
Thanks and Regards,
05-10-2018 08:03 AM
05-10-2018 10:23 PM
Thanks for your response. Sometimes one requires a 10 ms / 20 ms etc delays. For such feature, one requires to count the number of clock pulses. If the system clock is in MHz range, the size of the counter increases. So if I put a slow clock as a second clock input, this reduces the size of the counter.
05-11-2018 02:44 AM
that makes sense, there is also the clock divider that can divide from 2 to 16 times that may help slow the clock down more if needed