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One or more signals are missing in the process sensitivity list

Observer
Posts: 21
Registered: ‎02-15-2016

One or more signals are missing in the process sensitivity list

I am trying to write VHDL code for a circuit that acts as multiplier when sel=0 and acts as multiplier-accumulator when sel=1 with code as below

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity complex is
PORT
(
a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
sel: in std_logic;
clk: in std_logic;
prod: out std_logic_vector(31 downto 0)
);
end complex;

architecture Behavioral of complex is
signal product : std_logic_vector(31 downto 0);
signal multiply: std_logic_vector(31 downto 0);
signal Mux_Out: std_logic_vector(31 downto 0);
signal added: std_logic_vector(31 downto 0);

begin

multiply <= std_logic_vector(unsigned(a)*unsigned(b));
Mux_Out <= product when SEL='1' else 
"00000000000000000000000000000000";
added <= std_logic_vector(unsigned(multiply)+unsigned(Mux_Out));


process (clk)
begin
if(clk'EVENT and clk='1') then
product <= added;
end if;

prod <=product;
end process;


end Behavioral;

 

but when I try to synthesis this code it gives warning as below 

 

WARNING:Xst:819 -: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<product>

 

the issue is that when i simulate this code on isim, accumulator changes on falling edge of clock rather than rising edge of clock.

Scholar
Posts: 1,809
Registered: ‎07-09-2009

Re: One or more signals are missing in the process sensitivity list

well done for learning VHDL,

 

but

 

change the book your using...

 

clk'event died a long time ago, use rising_edge( clk ) instead.

 

carefull which libs you use,

 

http://vhdlguru.blogspot.co.uk/2010/03/why-library-numericstd-is-preferred.html

 

 

the process sensetivity list in enforced between the begin and end.

   so in your case , the sensitivity list is 'clk'

but your code says that prod depends upon product. 

 

It would be normal to do this sort of thing, 

   in one process

 

 

 

process rising_edge( clk )

begin

       if sel = '1' then

              { output depends upon something }

       else

              { output depends upon something else }

        end if;

  end process;

 

 

 

 

Observer
Posts: 21
Registered: ‎02-15-2016

Re: One or more signals are missing in the process sensitivity list

Thanks drjohnsmith for your reply. Changing clk'event to rising_edge(clk) produced exactly same result.

problem was solved by getting prod<=product out of process.

Explorer
Posts: 180
Registered: ‎04-12-2017

Re: One or more signals are missing in the process sensitivity list

[ Edited ]

Please notice that you have put a lot of functions as concurrent logic. Your design as you have done will have very tough timing problems.

 

Read a bit about pipelining and try to implement it in your design

Avi Chami MSc
FPGA Site
Highlighted
Instructor
Posts: 9,048
Registered: ‎08-14-2007

Re: One or more signals are missing in the process sensitivity list

I think what you missed from drjohnsmith's reply is that you typically have a process that only includes the clocked equations, rather than a mixed process, like yours, that has both sequential (clocked) and combinatorial equations.  In your process, "prod" is outside the clocked portion of the process.  Therefore it needs to have "product" (the only signal on the right side of the assignment) in the sensitivity list.  Note that if you add "product" to the sensitivity list, you should see "prod" update at the same time as "product," rather than at the next (falling) clock edge.  In behavioral simulation, the process only runs when something in the sensitivity list changes.  Assignments to signals inside a process are scheduled while the process runs, but only applied at the end of the process.  Thus when you make the assignment to "prod" inside the same process where you assign "product," that assignment will not update with the value of "product" that was assigned during this pass through the process.  Rather it takes on the value of "product" at the time the process was triggered to run.  Since you only have "clk" in the sensitivity list, the process will not re-run due to the change in value of "product," but only runs at any change in "clk."  Therefore you see "prod" change 1/2 clock cycle later.

 

Typically you should make a separate process for combinatorial assignments, or make the assignment outside of a process.  That way you don't run into this sort of warning.  In your case, I would typically place the assignment to "prod" outside of a process.  That is the equivalent of creating a separate process whose sensitivity list contains any signals used, in this case just "product."

 

If your intent was to use "prod" as an additional pipeline register, and have it change on the rising clock edge after "product," then it should be placed before the "end if" that closes the "if rising_edge(clk)" statement.

-- Gabor