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8,537 Views
Registered: ‎10-23-2013

Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

Hello everyone,

 

i’m new in the FPGA-Word and quite overwhelmed by the lack of good explanations hiding in a mountain of "information". So I hope someone can help me with my problem.

 

I want to generate a clock (e.g.. 200 MHz) from a 100 MHz Clock-input using the FPGAs internal clock generating functions. In my understanding by using the Clock Wizard a VHDL-Code should be generated that builds an instance of a PLL generating the needed clock signals.

 

Is this assumption correct?

 

While using the Clock Wizard i successfully synthesized the generated code and used PlanAhead to route the input and output signal (to measure the generated signal at an output IO). The "Implement Design"-Function produces 3 Errors, which are my problem: Place 1205, Place 1136 and Pack 1654.

 

Can you tell me why the ClockWizard produces faulty code and what I could change to be able to generate and output a certain clock?

 

Thank for your help!!

 

 

 

 

 

Here is the original Error-Message:

 

ERROR:Place:1205 - This design contains a global buffer instance, <clkout1_buf>,
   driving the net, <CLK_OUT1_OBUF>, that is driving the following (first 30)
   non-clock load pins off chip.
   < PIN: CLK_OUT1.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >


ERROR:Place:1136 - This design contains a global buffer instance, <clkout1_buf>,
   driving the net, <CLK_OUT1_OBUF>, that is driving the following (first 30)
   non-clock load pins.
   < PIN: CLK_OUT1.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >


ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

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8 Replies
Teacher eteam00
Teacher
8,523 Views
Registered: ‎07-21-2009

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

It looks like the problem is not the clock wizard code, but that you are trying to send the generated clock to an output pin via an obuf output buffer.  If this is the case, then please search the term 'clock forwarding' for the correct method of providing a clock signal on a device output pin.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Highlighted
Historian
Historian
8,521 Views
Registered: ‎01-23-2009

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

The error message you see here is one of the most explicit messages an FPGA tool will give you. It is telling you what the problem is, and how to solve it.

 

The clock wizard is generating code as it is supposed to - including instantiating (presumably) a global clock buffer on the output of the PLL. Clocks in an FPGA are "special things" - they have dedicated networks within the FPGA to distribute the clock to all clock pins of clockable cells. What you have done is try to connect this clock network to an output buffer, which is not a clock pin of a clockable cell. The error message is telling you this.

 

Furthermore, the error message is giving you the work-around. Rather than driving the clock to an output, you should use an ODDR to create a mirror of the clock. The ODDR is a clockable cell, and hence the clock net can be routed to it. Since it is an output double data rate flip-flop, it can put out two values each clock period - one after the rising edge of the clock (D1) and one after the falling edge of clock (D2). Therefore tying D1 to a 1 and D2 to a 0, will result in the output of the ODDR being 1 after the rising edge of the clock and a 0 after the falling edge of the clock - in other words a "mirror" of the clock.

 

This ODDR output can (in fact, must) be driven to an OBUF - the output buffer.

 

Avrum

8,506 Views
Registered: ‎10-23-2013

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

Thanks for this search term! I will try to understand the procedure to output the signal from the internal clock network.

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8,494 Views
Registered: ‎10-23-2013

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

Also thank you avrumw for your answer!!

 

Its an much better explanation than "tie the .D0 pin to Logic1; tie the .D1 pin toLogic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1." ;)

 

So the ClockWizard is generating an entity that enables an internal PLL and generating one or several Clock signals that are available on the internal clock bus. This Bus-Signal can either be routed to an ODDR(-entity??) and than to an IO-Pin or used in other internal components that are connected to the internal clock network. Is this correct?

 

Than I have to find out how to use the PLL-Signal in another entity that incorporates an ODDR or another kind of logic. 

 

The Wizard creates the following output buffer code:

 -- Output buffering
  -------------------------------------
  clkf_buf : BUFG
  port map
   (O => clkfb,
    I => clk2x);


  clkout1_buf : BUFG
  port map
   (O   => clk_out1_internal,
    I   => clk2x);


  CLK_OUT1 <= clk_out1_internal;

 

Is this the signal I can use (and how) in another entity to build an ODDR?

 

The Code for the ODDR on page 224 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/spartan6_hdl.pdf) has to be modified to me needs in some way I think.

 

 

 

p.s. "224" is the route of the problem ... XILINX makes a good job on endless pages describing what you can do, but not how to do it ^^. And I found no medium sized tutorial describing the usage of more than one entity or a PLL. Just little tutorials - easy to understand and fairly useless at this point :(

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Teacher eteam00
Teacher
8,487 Views
Registered: ‎07-21-2009

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

Don't give up, keep slogging through this.  Use the ISE checking tools to help learn the rules.  And you can use the technology schematic generator in ISE to help diagram the connections in the clock network.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
8,475 Views
Registered: ‎01-23-2009

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

I may understand the source of your problem...

 

The clock wizard is a tool to generate a component that is to be instantiated into your top level design - it is NOT a top level design unto itself.

 

I am now suspecting that you synthesized and implemented the clock wizard output alone. This is not an intended mechanism for what you are allowed to do.

 

However, when you asked for it, the tools tried. They realized that there were outputs of your  (now) "top level" design, and it attached an OBUF to it (which resulted int he error you saw).

 

So, the entity created by the clock wizard is always supposed to be instantiated as a component in some other top level entity. This top level entity is "your FPGA".

 

In the case of "your FPGA", you would need:

  - A top level definition

     - this includes entity declaration and input and output definitions

        - you would have one input - the input clock, and one output, the generated clock

  - Three instantiated components

    1) An instance of the clock wizard component. The tools actually help you with this by providing a .vho (I think that is the correct suffix) which is an example instantiation of the component in a top level design - cut lines from that and paste it into your top level, then customize the instance name and port connections. It even gives you the component declaration (which you need in VHDL)

    2) An instance of an ODDR, connected as described in the error message. The C0 and C1 would be connected to the output of the clock wizard (and the inverted version thereof). You can find the information for this in the User Guide for your FPGA (in the I/O chapter)

    3) An instand of an OBUF. The I input of the OBUF would be connected to the Q of the ODDR, and the O of the OBUF would be your top level output. Again, refer to the I.O chapter of the User Guide.

 

Then you should have a complete top level design, which you

   - should simulate

   - can synthesize, place, and route

   - can download to your board (if you have one) - and measure the outputs on an oscilloscope

 

Good luck.

 

Avrum

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8,444 Views
Registered: ‎10-23-2013

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

Thank you for your help and explanation!

 

I have routetd the Signal internally now. I just deleted the BUFG and it works (after reading and testing for hours ;) )

 

This solutions works and fits to my use-case. If I find the time I will test your solution to route the signal via PLL -> BUFG ->ODDR2 ->OBUF.

 

Until then ... thanks for your help!!

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8,397 Views
Registered: ‎10-23-2013

Re: Place-Error:1205, 1136, 1654 while using Clock Wizard generating PLL-Clock

Hello everyone

 

An additional question came up:

 

I want to use the DCM_SP-instance instead of the PLL to generate an internal Clock signal. Now the Place-Errors occurs again, even if - while using the PLL - everything worked fine.

 

What buffers (and why?) do I need in order to use the DCM instead of the PLL to generate an internal Clock signal?

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