06-27-2018 08:19 AM
WARNING:PhysDesignRules:372 - Gated clock. Clock net cam_2/clk_n is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
But the statement simple says assign clk_n = !clk;
whr both clk and clk_n are used in different modules separately.
What is the issue then.. how to create a clk_n in a correct way then????
06-27-2018 08:27 AM
You can clock a flip flop in an FPGA from either the rising or falling edges. There are few reasons to try to invert the clock. If you must, the DCM or a PLL should allow you to create a new clock with the desired phase shift.
06-29-2018 07:38 AM - edited 06-29-2018 07:40 AM
thanks for your response,
to generate a negated clk, i now use a negative edge triggered flip flop.
Firstly : why this issue doesnot occur when the clock is generated from clk_divider logic like follows?? is it becoz, it is the flip flop generating the divided clock??
initial // <= works in xilinx
Secondly the warning regarding Gated clock & combinatorial pin is also as below:
PhysDesignRules:372 - Gated clock. Clock net cam_2/m1/_n1251 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
cam_2/m1/_n1251 signal is generated by synthesis tool through LUT4, and doesnt exist in my verilog code, as can be checked in the post synthesis verilog file. I dont even know what I0, I1, I2 and I3 are, might require lot a back tracing, which might not a good debugging practice for a huge design.
I agree that a this portion of the code is generated through CASE statement, which is a combinational logic, but using case statement (with a default case) is also a valid verilog practice, isnt it??
.INIT ( 16'h4555 ))
Same applies to PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
I dont even know which net is icon_control0<13>. In case it is linked to chipscope in any way, i have generated chipscope through .cdc file , where there are only trigger ports visible and no icon_control0<13>.
How to trace the cause of such Gated Clock - combinatorial issues????
Thanks in advance..