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Visitor mkjaswal
Visitor
634 Views
Registered: ‎03-27-2017

Place & Route- DRC WARNING:PhysDesignRules:372 - Gated clock.

WARNING:PhysDesignRules:372 - Gated clock. Clock net cam_2/clk_n is sourced by a

   combinatorial pin. This is not good design practice. Use the CE pin to

   control the loading of data into the flip-flop.

 

 

But the statement simple says assign clk_n = !clk;

 

whr both clk and clk_n are used in different modules separately.

 

 

What is the issue then.. how to create a clk_n in a correct way then????

MKJ
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2 Replies
626 Views
Registered: ‎06-21-2017

Re: Place & Route- DRC WARNING:PhysDesignRules:372 - Gated clock.

You can clock a flip flop in an FPGA from either the rising or falling edges.   There are few reasons to try to invert the clock.  If you must, the DCM or a PLL should allow you to create a new clock with the desired phase shift.

Visitor mkjaswal
Visitor
577 Views
Registered: ‎03-27-2017

Re: Place & Route- DRC WARNING:PhysDesignRules:372 - Gated clock.

Hi 

thanks for your response, 

to generate a negated clk, i now use a negative edge triggered flip flop.

 

Firstly :  why this issue doesnot occur when the clock is generated from clk_divider logic like follows?? is it becoz, it is the flip flop generating the divided clock??

 

initial // <=  works in xilinx
begin
b=2'b0;
o_clk=1'b0;
end

always@(posedge clk)
begin
b<=b+2'b1;
o_clk<=b[1];
end

 

Secondly the warning regarding Gated clock & combinatorial pin is also as below:

 

PhysDesignRules:372 - Gated clock. Clock net cam_2/m1/_n1251 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 

cam_2/m1/_n1251 signal is generated by synthesis tool through LUT4, and doesnt exist in my verilog code, as can be checked in the post synthesis verilog file. I dont even know what I0, I1, I2 and I3 are, might require lot a back tracing, which might not a good debugging practice for a huge design.

 

I agree that a this portion of the code is generated through CASE statement, which is a combinational logic, but using case statement (with a default case) is also a valid verilog practice, isnt it??

 

LUT4 #(
.INIT ( 16'h4555 ))
\cam_2/m1/_n12511 (
.I0(\cam_2/m1/en_r_sel[33]_GND_6_o_equal_3_o ),
.I1(o_sel_9_OBUF_67),
.I2(\cam_2/m1/en_r_sel[33]_GND_6_o_equal_3_o<33>1 ),
.I3(\cam_2/m1/en_r_sel[33]_PWR_6_o_equal_29_o<33>2 ),
.O(\cam_2/m1/_n1251 )

 

 

Same applies to PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 

I dont even know which net is icon_control0<13>. In case it is linked to chipscope in any way, i have generated chipscope through .cdc file , where there are only trigger ports visible and no icon_control0<13>.

 

How to trace the cause of such Gated Clock - combinatorial issues????

 

Thanks in advance..

MKJ
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