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Adventurer
Adventurer
4,922 Views
Registered: ‎12-21-2011

Programmable Deserializer (8bit - 16bit) @ 500Mbit/s - Spartan 6

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Hi, in my design i need to incorporate programmable deserializer (LVDS DDR/SDR) capable to parallelize 8,10,12,14, or 16 bit serialized data. Maximum bitrate per channel is ~500Mbit/s.

I need to be able to configure the word length at run time (without programming whole device again). 

 

I did some reasearch, and those are my toughts:

 

1. I can't use only IOSERDES2's primitives becouse those are capable of deserializing up to 12 bit words ( with two IOSERDES2's per channel , master and slave)  -> xapp855.pdf 

 

2. There is configuration where i can deserialize more than 12bit words using IOSERDES2's but it needs a lot of logic and as far as i understand this solution is not as flexible as i need (8 to 16 bit words) -> xapp1064.pdf

 

3. The most flexible solution is to use BRAM to deserialize incoming data, it can be configure to parallelize up to 16 bit words, but i'm not sure if it will be capable to work at such high speeds, further more, the application note says that this solution is not recommended "Product Not Recommended for New Designs"  -> xapp690.pdf

 

4. Another possible solution is to write a simple 1-bit, 16bit - wide shift-register and drive it with bit clock, with simple programmable counter i could read from this register when desired number of bits was written into the register.

 

I'm just begining my FPGA journey and i'm not sure which solution is the best and how to find out which path i can choose.

 

Thanks for any help! 

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Teacher eteam00
Teacher
6,410 Views
Registered: ‎07-21-2009

Re: Programmable Deserializer (8bit - 16bit) @ 500Mbit/s - Spartan 6

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1. I can't use only IOSERDES2's primitives becouse those are capable of deserializing up to 12 bit words ( with two IOSERDES2's per channel , master and slave)  -> xapp855.pdf 

 

Spartan-6 SERDES blocks are 4-bit, not 6-bit.  So... up to 8 bit words, without help from fabric logic.

 

2. There is configuration where i can deserialize more than 12bit words using IOSERDES2's but it needs a lot of logic and as far as i understand this solution is not as flexible as i need (8 to 16 bit words) -> xapp1064.pdf

 

"but it needs a lot of logic" is not a reasonable characterisation, in my opinion.

 

The rest of your post is conclusions based on an undescribed application plus some conjecture.  The best response to these conclusions and conjectures is, simply, to code up your logic and let ISE have a go at it.  You will learn quite a bit in the process.

 

Or...  take a long look at reference designs.  XAPP495 is a good starting point, as this is the basis of the Digilent Atlys board reference design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
2 Replies
Teacher eteam00
Teacher
6,411 Views
Registered: ‎07-21-2009

Re: Programmable Deserializer (8bit - 16bit) @ 500Mbit/s - Spartan 6

Jump to solution

1. I can't use only IOSERDES2's primitives becouse those are capable of deserializing up to 12 bit words ( with two IOSERDES2's per channel , master and slave)  -> xapp855.pdf 

 

Spartan-6 SERDES blocks are 4-bit, not 6-bit.  So... up to 8 bit words, without help from fabric logic.

 

2. There is configuration where i can deserialize more than 12bit words using IOSERDES2's but it needs a lot of logic and as far as i understand this solution is not as flexible as i need (8 to 16 bit words) -> xapp1064.pdf

 

"but it needs a lot of logic" is not a reasonable characterisation, in my opinion.

 

The rest of your post is conclusions based on an undescribed application plus some conjecture.  The best response to these conclusions and conjectures is, simply, to code up your logic and let ISE have a go at it.  You will learn quite a bit in the process.

 

Or...  take a long look at reference designs.  XAPP495 is a good starting point, as this is the basis of the Digilent Atlys board reference design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Adventurer
Adventurer
4,906 Views
Registered: ‎12-21-2011

Re: Programmable Deserializer (8bit - 16bit) @ 500Mbit/s - Spartan 6

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Thanks Bob, i will take a long look at this app note i try to code up this by myself. 

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