04-19-2017 09:30 AM
I'm trying to use a LVDS differential input buffer (bank voltage is 3.3V) for a SLVS signal. According to XAPP894 it can be done by pulling down the common mode voltage via an external termination resistor (it also shows 2 LVCMOS inputs with 100 ohm series resistors for a LS mode). However, I have been ignoring the LS mode and only connected the SLVS lines to a LVDS_33 IBUFDS with 150 ohm external termination, but everything I get out of the differential buffer is '1' (and occasionally a bunch of '0's). The SLVS signals look as expected (swing between ca 100 mV and 300 mV).
I have never done something like this before, so I might miss or forgot something. Has someone done something like this before or any tips or ideas what the issue might be?
Thanks in advance.
04-19-2017 09:39 AM
If you are not using figure 6 (XAPP894) to interface, it will not work ....
Note that you have to solve the equations top set all the component values correctly.
04-19-2017 11:51 AM
@tidr1400 without the extra two resistors, the common mode shift will not happen. You need an equivalent structure even if you don't use them for LS signalling. Checkout lattice slvs appnotes, they have something similar to xapp without ls mode. It might help. Of course you can always simulate your design in spice and see what you get.
04-20-2017 02:49 AM
I was trying to find something in the Lattice app notes, but could find anything useful. Do you have a specific one in mind?
Also, I don't really know how to simulate it in Spice, especially with the LVCMOS signals.
We might just try connecting resistors to LVCMOS inputs (like in XAPP894 fig. 11) and see what happens.
11-27-2017 04:50 AM
figure 6 (XAPP894) is the case where FPGA works as the transceiver. How about receiver? Could I use figure11 with HR ports? Because in that pic, the I/O is LVDS_25_HR, but you also have 'IMPORTANT: External termination resistors must be used on LVDS configured I/O in high-performance (HP) I/O banks.' So I am confused.