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Visitor haunma
Visitor
5,384 Views
Registered: ‎03-21-2011

Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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I know the issue of power-supply sequencing has come up before, but my question is more specific:

 

Xilinx says there is no required sequencing between Vcco, Vccint, and Vccaux on Spartan 6.  At the same time, they still have a "recommended" sequence, and the datasheet doesn't specify things like quiescent current on some power pins when other power pins are at 0V.

 

I'm designing a Spartan-6 daughterboard with 3.3, 2.5, 1.8, and 1.2-volt power requirements.  The 1.8V is Vcco for a couple of IO banks.  I'll have my own power supply (from 5V) for all but the 1.8V rail.  This I plan on grabbing from an expansion connector I'm plugging into.  The other rails won't come up until commanded via i2c.  What this means is that the FPGA could see Vcco powered for a long time--potentially hours or days--before Vccint and Vccaux come online.  By a literal reading of the Xilinx docs, this is fine.  But it makes me a bit nervous, because I don't have a spec for the quiescent power on Vcco when the other supplies are zero, and because most discussion of power sequencing is in the context of microseconds or milliseconds, not kiloseconds.

 

Any words of caution (substantiated by reasons why)?

 

Thanks.

 

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Xilinx Employee
Xilinx Employee
6,829 Views
Registered: ‎07-30-2007

Re: Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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The S-6 recomendation of Vccint first is becuase when Vcco is powerd first the pullups may be enabled in the IOs.  Now, if there are a lot of pulldowns on the board this is where the quiesent current will come from .  You should be able to measure this and it should be static over time.  30 sec after power up should be the same as 30 days after power up of Vcco only.

 

The parts are really robust and I wouldn't worry about the S-6 part at all on this one and as long as you measure the current on the power rail you should have a good understanding of how the parts will behave. 

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Visitor haunma
Visitor
5,353 Views
Registered: ‎03-21-2011

Re: Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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Is there a Xilinx engineer in the house?

 

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Historian
Historian
5,350 Views
Registered: ‎02-25-2008

Re: Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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@haunma wrote:

Is there a Xilinx engineer in the house?

 


If immediate answers are required, contact your local FAE or open a WebCase.

 

----------------------------Yes, I do this for a living.
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Visitor haunma
Visitor
5,348 Views
Registered: ‎03-21-2011

Re: Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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Thanks bassman, I will pursue a WebCase, but I thought the answer might be of general interest.  I don't need an immediate answer, but I was kinda hoping for *an* answer :)

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Xilinx Employee
Xilinx Employee
6,830 Views
Registered: ‎07-30-2007

Re: Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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The S-6 recomendation of Vccint first is becuase when Vcco is powerd first the pullups may be enabled in the IOs.  Now, if there are a lot of pulldowns on the board this is where the quiesent current will come from .  You should be able to measure this and it should be static over time.  30 sec after power up should be the same as 30 days after power up of Vcco only.

 

The parts are really robust and I wouldn't worry about the S-6 part at all on this one and as long as you measure the current on the power rail you should have a good understanding of how the parts will behave. 

Visitor haunma
Visitor
5,319 Views
Registered: ‎03-21-2011

Re: Spartan 6 power design with Vcco applied long before Vccint, Vccaux

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Thanks!  That's what I needed to know.

 

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