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Observer
459 Views
Registered: ‎07-20-2018

problem with concept of bus big-end and little-end in WIRE vs REG

hello .i wrote a code in verilog and it is look that bus of wire is different from bus of reg for example

```reg        [0 : 31]           slv_reg0;initial slv_reg0=1;
always * begin
led=slv_reg0[31];
end ```

in this case lsb in led will be on (led is connected to 31 led)

but when i write this code

```wire        [0 : 31]           my_wire;assign my_wire[31]=1;
assign	led =my_wire;

```

the msb of led is on

what is the reason?????

1 Solution

Accepted Solutions
Historian
466 Views
Registered: ‎01-23-2009

Re: problem with concept of bus big-end and little-end in WIRE vs REG

Your two pieces of code are not the functionally the same.

First, you need to understand that the way you declare a bus matters... Buses are always most significant on the right and least significant on the left. The numbers you use when you declare the bus merely give names to the bits. So when you use

reg [0:31] busa;

you are "naming" the rightmost (always least significant) bit as 31 and the most significant bit as 0.

When you go

reg [31:0] busb;

You are naming the rightmost (still least signifacant) bit as 0 at the most significant bit as 31

So for slv_reg0, you are giving the entire bus the value 1, which means 0 in all the MSbit and a 1 in the LSbit, which is named 31. So when you assign led to slv_reg0[31] you get the only 1.

For my_wire, you are doing the opposite. You are assigning only bit 31 (again the leftmost or least significant bit) to a 1 (and leaving the others unassigned, which will make them Z), You are ten assigning the (presumably) one bit wire led to my_wire; the leftmost (least significant) bit gets assigned to the only bit of led (which is a 1), and the remaining 31 bits are truncated due to the size mismatch.

So, yes, led is 1 in both cases.

NOTE: This has nothing to do with "endian". Big-endian vs. little-endian refers to how a multiple byte word mapped into byte addresses. In binary representation the least significant bit is always on the right.

Avrum

Historian
467 Views
Registered: ‎01-23-2009

Re: problem with concept of bus big-end and little-end in WIRE vs REG

Your two pieces of code are not the functionally the same.

First, you need to understand that the way you declare a bus matters... Buses are always most significant on the right and least significant on the left. The numbers you use when you declare the bus merely give names to the bits. So when you use

reg [0:31] busa;

you are "naming" the rightmost (always least significant) bit as 31 and the most significant bit as 0.

When you go

reg [31:0] busb;

You are naming the rightmost (still least signifacant) bit as 0 at the most significant bit as 31

So for slv_reg0, you are giving the entire bus the value 1, which means 0 in all the MSbit and a 1 in the LSbit, which is named 31. So when you assign led to slv_reg0[31] you get the only 1.

For my_wire, you are doing the opposite. You are assigning only bit 31 (again the leftmost or least significant bit) to a 1 (and leaving the others unassigned, which will make them Z), You are ten assigning the (presumably) one bit wire led to my_wire; the leftmost (least significant) bit gets assigned to the only bit of led (which is a 1), and the remaining 31 bits are truncated due to the size mismatch.

So, yes, led is 1 in both cases.

NOTE: This has nothing to do with "endian". Big-endian vs. little-endian refers to how a multiple byte word mapped into byte addresses. In binary representation the least significant bit is always on the right.

Avrum