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Explorer
Explorer
1,083 Views
Registered: ‎03-08-2018

spartan6lx16 ft256-C2 clocking question

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Dear All,

 

I'm trying to understand pll clocking setting.

 

the reference original code is the below

 

 

 original used 100Mhz input clock,
and make 150Mhz. and set as the below.

clocking clocking_block( .CLK_IN(CLK), .CLK_OUT(pclk)); // PLL called to get x10 and x5 clock from the Pixel clock. PLL_BASE # ( .CLKIN_PERIOD(10), .CLKFBOUT_MULT(10), .CLKOUT0_DIVIDE(1), .CLKOUT1_DIVIDE(10), .CLKOUT2_DIVIDE(5), .COMPENSATION("SOURCE_SYNCHRONOUS") ) PLL_OSERDES_0 ( .CLKFBOUT(clkfbout), .CLKOUT0(pllclk0), .CLKOUT1(), .CLKOUT2(pllclk2), .CLKOUT3(), .CLKOUT4(), .CLKOUT5(), .LOCKED(plllckd), .CLKFBIN(clkfbin), .CLKIN(pclk), .RST(pll_reset) );

 

Currently my target board set as the below

 

On-Board FPGA: XC6SLX16-2FTG256C;
On-Board FPGA external crystal frequency: 50MHz;

and I make a 150Mhz output clock signal from 50Mhz in clocking block

 

 

But I want to know What value do I set the parameter correctly in ".CLKIN_PERIOD( ? )? and CLKBOUT_MULT( ? )?

 

  PLL_BASE # (
    .CLKIN_PERIOD( ? ),
    .CLKFBOUT_MULT( ? ), 
    .CLKOUT0_DIVIDE(1),
    .CLKOUT1_DIVIDE(10),
    .CLKOUT2_DIVIDE(5),
    .COMPENSATION("SOURCE_SYNCHRONOUS")

 

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Xilinx Employee
Xilinx Employee
1,386 Views
Registered: ‎08-07-2007

回复: spartan6lx16 ft256-C2 clocking question

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hi @love119

 

You can manually select the primivite type.

Please see the snapshot below.

 

Thanks,

Boris

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pll_base.png
9 Replies
Xilinx Employee
Xilinx Employee
1,073 Views
Registered: ‎08-07-2007

回复: spartan6lx16 ft256-C2 clocking question

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hi @love119

 

you can refer to UG382.pdf to understand the settings.

 

the simpler way is to use Clocking Wizard IP to generate the wrapper.

simply enter the input frequency and output expectation, it will generate the clocking design for you.

 

Thanks,

Boris

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Explorer
Explorer
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Registered: ‎03-08-2018

回复: spartan6lx16 ft256-C2 clocking question

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@borisq  Thanks But I can't find that " PLL_OSERDES_0  " from clocking wizard of coregen

 

How do I get the below module from coregen?

 

  PLL_BASE # (
    .CLKIN_PERIOD(10),
    .CLKFBOUT_MULT(10), 
    .CLKOUT0_DIVIDE(1),
    .CLKOUT1_DIVIDE(10),
    .CLKOUT2_DIVIDE(5),
    .COMPENSATION("SOURCE_SYNCHRONOUS")
  ) PLL_OSERDES_0 (
    .CLKFBOUT(clkfbout),
    .CLKOUT0(pllclk0),
    .CLKOUT1(),
    .CLKOUT2(pllclk2),
    .CLKOUT3(),
    .CLKOUT4(),
    .CLKOUT5(),
    .LOCKED(plllckd),
    .CLKFBIN(clkfbin),
    .CLKIN(pclk),
    .RST(pll_reset)
  );
  
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: spartan6lx16 ft256-C2 clocking question

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hi @love119

 

“PLL_OSERDES_0”is the instantiation name. Just a name. 

You can rename it to anything, like PLL_OSERDES_1, PLL_OSERDES_A, my_clocking, etc...

 

If you want an IP with that name, just enter PLL_OSERDES_0 in the Component Name field when custermizing the IP.

 

Thanks,

Boris

 

 

 

 

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Explorer
Explorer
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Registered: ‎03-08-2018

回复: spartan6lx16 ft256-C2 clocking question

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@borisq

 

Sorry for my typo.PLL_BASE not instantiation name.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: spartan6lx16 ft256-C2 clocking question

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hi @love119

 

You can manually select the primivite type.

Please see the snapshot below.

 

Thanks,

Boris

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pll_base.png
Explorer
Explorer
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Registered: ‎03-08-2018

回复: spartan6lx16 ft256-C2 clocking question

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@borisq Can I ask you more in here? or should I have to make another question?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: spartan6lx16 ft256-C2 clocking question

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hi @love119

 

if there is some connection with the original question, you can ask here.

if not, you can ask a new question.

 

Thanks,

Boris

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Explorer
Explorer
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回复: spartan6lx16 ft256-C2 clocking question

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Thanks you @borisq

 

I found the some warning message when I make a clock by using clocking wizard.

 

"CLK_OUT2 frequency requires that this output clock must drive a BUFPLL"

 

q108.JPG

 

 

But I can't find any BUFFPLL instantiation (

 

such as BUFPLL #(.DIVIDE(5)) ioclk_buf (.PLLIN(pllclk0), .GCLK(pclkx2), .LOCKED(plllckd),
.IOCLK(pclkx10), .SERDESSTROBE(serdesstrobe), .LOCK(bufpll_lock));

 

) from generated file.

 

// file: pll_clk.v
// 
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
// 
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
// 
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
// 
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
// 
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// 
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___150.015______0.000______50.0______157.321____178.205
// CLK_OUT2___750.075______0.000______50.0______115.172____178.205
//
//----------------------------------------------------------------------------
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_____________150____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "pll_clk,clk_wiz_v3_6,{component_name=pll_clk,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=6.666,clkin2_period=6.666,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=true}" *)
module pll_clk
 (// Clock in ports
  input         CLK_IN1,
  // Clock out ports
  output        CLK_OUT1,
  output        CLK_OUT2,
  // Status and control signals
  input         RESET,
  output        LOCKED
 );

  // Input buffering
  //------------------------------------
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));


  // Clocking primitive
  //------------------------------------
  // Instantiation of the PLL primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        clkfbout;
  wire        clkfbout_buf;
  wire        clkout2_unused;
  wire        clkout3_unused;
  wire        clkout4_unused;
  wire        clkout5_unused;

  PLL_BASE
  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (5),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (5),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKOUT1_DIVIDE         (1),
    .CLKOUT1_PHASE          (0.000),
    .CLKOUT1_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (6.666),
    .REF_JITTER             (0.010))
  pll_base_inst
    // Output clocks
   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (clkout1),
    .CLKOUT2               (clkout2_unused),
    .CLKOUT3               (clkout3_unused),
    .CLKOUT4               (clkout4_unused),
    .CLKOUT5               (clkout5_unused),
    // Status and control signals
    .LOCKED                (LOCKED),
    .RST                   (RESET),
     // Input clock control
    .CLKFBIN               (clkfbout_buf),
    .CLKIN                 (clkin1));


  // Output buffering
  //-----------------------------------
  BUFG clkf_buf
   (.O (clkfbout_buf),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));


  assign CLK_OUT2 = clkout1;



endmodule

Should I have to modify that file by manually? If I need it then would you please guide me?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: spartan6lx16 ft256-C2 clocking question

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hi @love119

 

i think this should be a new questions.

 

please put it in a new thread.

 

thanks,

Boris

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