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Visitor afcika3092
Visitor
1,158 Views
Registered: ‎07-09-2019

0 Utilization after synthesis. Design has unconnected ports

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So, I am building a MIPS processor in Verilog and I am have some progress. So far, the design simulates and I am able to observe some correct results. However, when I try to synthesize the code, it is successful but under "Design Runs", I get "0 FF, 0 LUT", basically zero everything; it seems like it ignores all the components in the design. The design also has some warnings after synthesis:

[Synth 8-3331] design DM has unconnected port i_dma[31]
[Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.


 My top-level module (MIPS takes only clock input. This module interconnects all the modules in the design):

`timescale 1ns / 1ps
`default_nettype none


module MIPS_single_cycle_processor(
    input wire i_clk
    );
/* END OF PARAMETERS */
  
/* REG/WIRE declarations  */
    wire [31:0] Inst;       // value coming out of IM. Holds 32-bit instruction
    supply0 constant_0;     // modules not being reset (PC)
    
    // instruction part-selects
    wire [5:0] opcode = Inst[31:26];
    wire [4:0] rs = Inst[25:21];
    wire [4:0] rt = Inst[20:16];
    wire [4:0] rd = Inst[15:11];
    wire [15:0] Imm = Inst[15:0];
    wire [5:0] funct = Inst[5:0];
    wire [25:0] Jaddr = Inst[25:0];
    // END OF instruction part-selects
    
/* RF input/output buffer wires*/
    
    // register file input buffer wires
    wire [4:0] RFWA;
    // END of register file input buffer wires

    // register file output buffer wires
    wire [31:0] RFRD1;
    wire [31:0] RFRD2;
    // END of register file output buffer wires

/* END OF RF input/output buffer wires*/


/* ALU input/output buffer wires*/
    // ALU input buffer wires
    wire [31:0] ALIIn2;
    // END of ALU input buffer wires
    
    // ALU output buffer wires
    wire [31:0] ALUOut;
    // END of ALU output buffer wires
/* END OF ALU input/output buffer wires*/


/* SE input/output buffer wires*/
    // SE input buffer wires
    
    // END of SE input buffer wires
    
    // SE output buffer wires
    wire [31:0] Simm;
    // END of SE output buffer wires
/* END OF SE input/output buffer wires*/


/* PC input/output buffer wires*/
    // PC input buffer wires
    wire [31:0] i_pc_adder_int;    // value coming out of PC going into PC adder
    // END of PC input buffer wires
    
    // PC output buffer wires
    wire [31:0] o_pc_adder_int;    // value coming out of PC adder going into PC
    // END of PC output buffer wires
/* END OF PC input/output buffer wires*/


/* PCBranch input/output buffer wires*/
    // PCBranch input buffer wires
    
    // END of PCBranch input buffer wires
    
    // PCBranch output buffer wires
    wire [31:0] PCBranch;
    // END of PCBranch output buffer wires
/* END OF PCBranch input/output buffer wires*/


/* BCBranch out mux input/output buffer wires*/
    // BCBranch out mux input buffer wires
    
    // END of BCBranch out mux input buffer wires
    
    // BCBranch out mux output buffer wires
    wire [31:0] BCBranch_out_mux_int;
    // END of BCBranch out mux output buffer wires
/* END OF BCBranch out mux input/output buffer wires*/


/* PCSel AND gate input/output buffer wires*/
    // PCSel AND gate input buffer wires
    
    // END of PCSel AND gate input buffer wires
    
    // PCSel AND gate output buffer wires
    wire PCSel;
    // END of PCSel AND gate output buffer wires
/* END OF PCSel AND gate input/output buffer wires*/


/* PC input ultimate mux input/output buffer wires*/
    // PC input ultimate mux input buffer wires
    
    // END of PC input ultimate mux input buffer wires
    
    // PC input ultimate mux output buffer wires
    wire [31:0] PC_final_mux_out;
    // END of PC input ultimate mux output buffer wires
/* END OF PC input ultimate mux input/output buffer wires*/


/* DM input/output buffer wires*/
    // DM input buffer wires
    
    // END of DM input buffer wires
    
    // DM output buffer wires
    wire [31:0] DMOut;
    // END of DM output buffer wires
/* END OF DM input/output buffer wires*/

/* END OF REG/WIRE declarations  */


/* DM out mux input/output buffer wires*/
    // DM out mux input buffer wires
    
    // END of DM out mux input buffer wires
    
    // DM out mux output buffer wires
    wire [31:0] ALUDM;
    // END of DM out mux output buffer wires
/* END OF DM out mux input/output buffer wires*/

/* END OF REG/WIRE declarations  */


/* CONTROL SIGNALS */
    wire RFWE;
    wire [2:0] ALUsel;
    wire ALUInSel;
    wire RFDSel;
    wire MtoRFSel;
    wire DMWE;
    wire Branch;
    wire Jump;
    
/* END OF CONTROL SIGNALS */

/* flaps set */
    wire Zero;
/* END OF flaps set */
    
    
    
/* STRUCTURAL CODING, i.e., interconnecting CPU modules */
    
    // ALU instantiation
    ALU ALU_instance (.i_ALU_1(RFRD1), .i_ALU_2(ALIIn2), .i_ALU_sel(ALUsel),
                        .o_zero_f(Zero), .o_ALU(ALUOut));
    // mux at ALUIn2 input
    mux_2_to_1 #(.MUX_DATA_WIDTH(32)) ALUIn2_mux (.i_A(RFRD2), .i_B(Simm), .i_sel(ALUInSel), .o_mux(ALIIn2));
    
    // data memory instantiation
    DM DM_instance (.i_dma(ALUOut), .i_dmwd(RFRD2), .i_dmwe(DMWE), .i_clk(i_clk), .o_dmrd(DMOut));
    // DM out mux
    mux_2_to_1 #(.MUX_DATA_WIDTH(32)) DM_out_mux(.i_A(ALUOut), .i_B(DMOut), .i_sel(MtoRFSel), .o_mux(ALUDM));
    
    // Instruction Memory instantiation
    IM IM_instance (.i_ima(i_pc_adder_int), .o_imrd(Inst));
    
    // 16_bit to 32_bit sign extension module
    SE SE_instance(.i_imm(Imm), .o_simm(Simm));
    
    // program counter
    PC PC_instance(.i_pc(PC_final_mux_out), .i_rst(constant_0), .i_clk(i_clk), .o_pc(i_pc_adder_int));
    // adder that adds 1 to program counter
    PC_adder PC_adder_instance (.i_pc_adder(i_pc_adder_int), .o_pc_adder(o_pc_adder_int));
    
    // register file instantiation
    RF RF_instance(.i_rfra1(rs), .i_rfra2(rt), .i_rfwa(RFWA), .i_rfwd(ALUDM), 
                    .i_rfwe(RFWE), .i_clk(i_clk), .o_rfrd1(RFRD1), .o_rfrd2(RFRD2) );
    // mux at RF RFWA input
    mux_2_to_1 #(.MUX_DATA_WIDTH(5)) RFWA_mux(.i_A(rt), .i_B(rd), .i_sel(RFDSel), .o_mux(RFWA));

    // PCBranch 32-bit adder
    adder_32_bit adder_32_bit_instance(.i_A(Simm), .i_B(o_pc_adder_int), .o_add(PCBranch));
    
    // BCBranch out mux
    mux_2_to_1 #(.MUX_DATA_WIDTH(32)) BCBranch_out_instance(.i_A(o_pc_adder_int), .i_B(PCBranch), .i_sel(PCSel), .o_mux(BCBranch_out_mux_int));
    
    // PC input ultimate mux
    mux_2_to_1 #(.MUX_DATA_WIDTH(32)) PC_in_mux(.i_A(BCBranch_out_mux_int), .i_B({o_pc_adder_int[31:26], Jaddr}), .i_sel(Jump), .o_mux(PC_final_mux_out));
    
    // PCSel AND gate
    and(PCSel, Branch, Zero);
    
    // Control Unit instantiation
    CU CU_instance(
    .i_opcode(opcode),
    .i_funct(funct),
    .o_MtoRFSel(MtoRFSel),
    .o_DMWE(DMWE),
    .o_Branch(Branch),
    .o_ALUInSel(ALUInSel),
    .o_RFDSel(RFDSel),
    .o_RFWE(RFWE),
    .o_Jump(Jump),
    .o_ALUsel(ALUsel));
    
/* END OF STRUCTURAL CODING */
endmodule

DM module (which has an unconnected port after synthesis):

module DM(
    input wire [31:0] i_dma,
    input wire [31:0] i_dmwd,
    input wire i_dmwe,
    input wire i_clk,
    output reg [31:0] o_dmrd
    );
    
    // data memory ram declaration
    reg [31:0] DM_ram [0:512];
        
    initial $readmemb("DM_test_data.mem", DM_ram, 0, 100);    
        
    // handles asynchronous data read
    always @(*) begin
        o_dmrd = DM_ram[i_dma];
    end
    
    // handles synchronous data write
    always @(posedge i_clk) begin
        if(i_dmwe) begin
            DM_ram[i_dma] <= i_dmwd;
        end
    end
    
endmodule

Anyone have any suggestions?

 

Thank you very much

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Scholar u4223374
Scholar
1,142 Views
Registered: ‎04-26-2015

Re: 0 Utilization after synthesis. Design has unconnected ports

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Your top module has no outputs. Vivado (or ISE?) is recognising (correctly) that the behaviour of this system will be absolutely identical to the behaviour of an empty FPGA. So it optimizes the design for minimum power and resource usage simply by deleting everything.

 

Any practical system is going to need some sort of output, and when you add an output that actually depends on the system then Vivado will stop removing your whole project.

 

 

6 Replies
Highlighted
Scholar u4223374
Scholar
1,143 Views
Registered: ‎04-26-2015

Re: 0 Utilization after synthesis. Design has unconnected ports

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Your top module has no outputs. Vivado (or ISE?) is recognising (correctly) that the behaviour of this system will be absolutely identical to the behaviour of an empty FPGA. So it optimizes the design for minimum power and resource usage simply by deleting everything.

 

Any practical system is going to need some sort of output, and when you add an output that actually depends on the system then Vivado will stop removing your whole project.

 

 

1,136 Views
Registered: ‎07-23-2019

Re: 0 Utilization after synthesis. Design has unconnected ports

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That warning could indicate something has been optimized out (deleted).

Have you selected the right file as top? (It happens to me all the time..)

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Visitor afcika3092
Visitor
1,130 Views
Registered: ‎07-09-2019

Re: 0 Utilization after synthesis. Design has unconnected ports

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Yes, I created this file exactly with that intent, to use it as top-level module, and I also specified it to be used for synthesis and implementation in Vivado. I added some outputs to the top-level module as the other posted suggested, and I am getting some utilization so that works. But, I am still getting the "Unconnected Port" warning.

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Moderator
Moderator
1,127 Views
Registered: ‎03-16-2017

Re: 0 Utilization after synthesis. Design has unconnected ports

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Hi @afcika3092

In your DM module just add dont_touch attribute as shown below which will preserve your 32 bit input. 

(* dont_touch = "yes" * ) input wire [31:0] i_dma,

 

Regards,
hemangd

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Visitor afcika3092
Visitor
1,113 Views
Registered: ‎07-09-2019

Re: 0 Utilization after synthesis. Design has unconnected ports

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That solved the "Unconnected Port" problem! Thanks a lot. How do I accept more than one reply as a solution :D

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Moderator
Moderator
1,064 Views
Registered: ‎03-16-2017

Re: 0 Utilization after synthesis. Design has unconnected ports

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Hi @afcika3092

You can only select one reply and mark it as an accepted solution. 

Kindly close the thread by marking one answer as an accepted solution which helped you most to resolve your queries. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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