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Registered: ‎11-23-2009

2 process fsm not inferred when 'next state' signal initialized

I'm porting designs from ISE to Vivado, and found that all my fsm's which ISE detected without problems where not detected by vivado (see posting). Took some time to find why, the reason is strange indeed and might explain some of the problems others had.


I use, for very good reasons, a 2 state machine coding. There is a sequential process which just describes the state register and the reset logic. And a combinatorial process which has the next state logic and the output logic. Naturally there is a signal to communicate the 'next state' from the combinatorial to the sequential process.


It turns out that


  Vivado does not infer a FSM when the 'next state' signal is initiallized !


The pertinent part of the code is


   architecture arch of simple2p is

     type t_state is (s_halt, s_sdata,...);

     signal current_state : t_state := s_halt;
     signal next_state : t_state;        -- MUST NOT BE INITIALIZED !!!


       if rising_edge(clk) then
          if rst = '1' then
             current_state <= s_halt;
             current_state <= next_state;
          end if;
       end if;
    end process;

    process(current_state, ...)

       case current_state is



Such a fsm is propperly inferred !!


But if one writes instead


     signal next_state : t_state := s_halt;


or what many would do


     signal current_state, next_state : t_state := s_halt;


than the fsm is not inferred !!


  A simple initialization of a combinatorial signal (aka wire) prevents fsm inferrence.


Really difficult to understand because this initialization has no effect. But since many folks have the habit initialize all signals it is frequently done. With very surprising side effect.


The attached tar ball has an example, and two log files. One taken with 'next_state' un-initialized, the other with 'next_state' initiallized.


And for the record: this behaviour is in Vivado 2014.4 (tested) to 2016.1 (tested).