01-29-2016 12:11 PM
I am currently working on a project which i will describe. I have a vhdl source code (eg the bft core from the Planahead examples) and I synthesize and implement it using Planahead. Then, I analyze it using a tool I developed and I find some signals that control the paths. After that, I want to add some logic to the above circuit but it is crusial for me the previous design to remain exactly the same. I tried doing that with partisions. However, I faced some problems.
1) Planahead does not allow me to set as partision all primitives used (muxes and latches). I want, however, all of them to remain unchanged. So, how can I lock these primitives, too? Is that possible?
2) How can I make my two partisions (supposing that the added logic is a new partision) interact?
I read some of Xilinx's tutorials but I found them too unfathomable for me to understand.
Any simpler tutorial or example would be highly appreciated.
Please let me know if you need more information about my project.
Thanks a lot,
01-29-2016 07:13 PM
Please go through the following tutorial
01-30-2016 11:15 AM - edited 01-31-2016 02:02 AM
It seems there is a problem with the Xilinx servers as I cannot download anything, even after google search. I hope it gets fixed soon.
Thanks arpansur, when I am able to download to, i will inform you
Edit: I read that tutorial. It is not exactly what I am looking for. I want to lock the entilre circuit (including primitives and nets), so that delays and timing remain the same.