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Adventurer
Adventurer
7,489 Views
Registered: ‎07-13-2014

2 questions about partisions

Hello everyone.

 

I am currently working on a project which i will describe. I have a vhdl source code (eg the bft core from the Planahead examples) and I synthesize and implement it using Planahead. Then, I analyze it using a tool I developed and I find some signals that control the paths. After that, I want to add some logic to the above circuit but it is crusial for me the previous design to remain exactly the same. I tried doing that with partisions. However, I faced some problems.

1) Planahead does not allow me to set as partision all primitives used (muxes and latches). I want, however, all of them to remain unchanged. So, how can I lock these primitives, too? Is that possible?

2) How can I make my two partisions (supposing that the added logic is a new partision) interact?

 

I read some of Xilinx's tutorials but I found them too unfathomable for me to understand.

Any simpler tutorial or example would be highly appreciated.

Please let me know if you need more information about my project.

 

Thanks a lot,

Peter 

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2 Replies
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Moderator
Moderator
7,460 Views
Registered: ‎07-01-2015

Hi @pesous,

 

Please go through the following tutorial
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/PlanAhead_Tutorial_Partial_Reconfiguration.pdf

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
7,344 Views
Registered: ‎07-13-2014

 It seems there is a problem with the Xilinx servers as I cannot download anything, even after google search. I hope it gets fixed soon.

 

Thanks arpansur, when I am able to download to, i will inform you

 

Edit: I read that tutorial. It is not exactly what I am looking for. I want to lock the entilre circuit (including primitives and nets), so that delays and timing remain the same.

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