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Participant
Participant
2,913 Views
Registered: ‎08-15-2016

2016.2 Synthesis error- regarding module contain entity which was created in system generator

I got the following error when I execute Synthesis

[Synth 8-3493] module 'decore_bd' declared at 'C:/project/syn/syn.runs/synth_1/.Xil/Vivado-10060-proj/realtime/decore_bd_stub.vhdl:5' does not have matching formal port for component port 'tl_out' ["C:/project/ip_repo/bd/decore_bd/hdl/decore_bd_wrapper.vhd":127]

 

decore_bd_wrapper is a wrapper which contain module which was created in system generator

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Moderator
Moderator
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Registered: ‎09-15-2016

Re: 2016.2 Synthesis error- regarding module contain entity which was created in system generator

Hi @sarit8

 

Looks like port declared in the module 'decore_bd' and instantiated as the component declaration in the wrapper file are different.

Make sure that the component file and the top level file have the same ports instantiated and used.

 

From sources view you can open design_1_wrapper.vhd and design_1 and see if there is a port mismatch between them. if it is the case, regenerate the wrapper by removing the old one from project, then create a new HDL wrapper by clicking the block design in the sources view.

 

Hope the shared information helps.

 

Regards

Rohit

 

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Regards
Rohit
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Moderator
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Registered: ‎09-15-2016

Re: 2016.2 Synthesis error- regarding module contain entity which was created in system generator

Hi @sarit8,

 

Check if port is declared in module instantiation for 'tl_out' in decore_bd_stub.vhdl.

 

Regards,
Prathik
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Moderator
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Registered: ‎09-15-2016

Re: 2016.2 Synthesis error- regarding module contain entity which was created in system generator

Hi @sarit8

 

Did the given suggestions helped? Let me know if you face any issues.

 

Regards

Rohit

 

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Regards
Rohit
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