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Visitor
Visitor
701 Views
Registered: ‎02-14-2019

2017.4 Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) synthesis

I attempt to synthesis my project on a Windows 64 bit machine and get the following error:

Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check '.../synth_1/hs_err_pid9364.log' for details

The Log file states the following:

#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

Analyzing the .dmp file I see the following:

This dump file has an exception of interest stored in it.
The stored exception information can be accessed via .ecxr.
(2494.2894): Access violation - code c0000005 (first/second chance not available)
*** ERROR: Symbol file could not be found. Defaulted to export symbols for ntdll.dll -
ntdll!ZwGetContextThread+0xa:
00000000`7747a55a c3 ret
0:001> .ecxr
rax=0000000000000000 rbx=000000002fddd6e0 rcx=000000002fddd6e0
rdx=000000002fddd6e0 rsi=000000001b8879c0 rdi=00000000203865d0
rip=000007feb5cfb3db rsp=0000000003c91210 rbp=0000000003c91370
r8=0000000000000000 r9=000000000c9123e0 r10=0000000003c911e0
r11=0001da95059c00d3 r12=000000000c9123e0 r13=0000000003c916a0
r14=0000000013233848 r15=0000000013233820
iopl=0 nv up ei pl nz na po nc
cs=0033 ss=002b ds=002b es=002b fs=0053 gs=002b efl=00010206
*** ERROR: Symbol file could not be found. Defaulted to export symbols for librdi_synth.dll -
librdi_synth!NloptVerilogReader::verilogReader::verilogReaderAssert+0x61a05b:
000007fe`b5cfb3db 488b4008 mov rax,qword ptr [rax+8] ds:00000000`00000008=????????????????

what can I do for my project?

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11 Replies
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Xilinx Employee
Xilinx Employee
675 Views
Registered: ‎05-14-2008

Could you show us the Synthesis report or the last lines in the log window?

And a general debugging method of this kind of issue can be found in below blog:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Vivado-Synthesis-Crash-Debugging-Guide/ba-p/946862

-vivian

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Visitor
Visitor
641 Views
Registered: ‎02-14-2019

thank you for your help, vivian.

The problem disappears, just cause I modify the number of the instances. It is a little strange.

In the project, I set up 8 slaves instances of the same module. The problem happenes at the first time when I synthesis it. Then, I synthesis the project by comments 4 instances, by comments 3 instances, by comments 2 instances, by comments 1 instance, but no problems happens. 

At last, I repair the project, and no problmes happens.By the way, the top level module has more than 2000 wires, does it make sense?

Another problem is happenning. The LUT utilization of Post-Synthesis for 5 slaves is 19%, but it is 77% for 8 slaves. The LUT utilization increases unlinearly.

The target device is xc7z020clg484-1. And synthesis strategy is Vivado Synthesis Defaults(Vivado Synthesis 2017).

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Moderator
Moderator
632 Views
Registered: ‎03-16-2017

Hi @mario.niu , 

>>The problem disappears, just cause I modify the number of the instances. It is a little strange.

Can you check with the latest Vivado version 2019.1 ? It might possible that this issue got fixed with this latest version. And you can use your design without any instance modification. 

If the crash persists even with latest Vivado version, please share the design with us so we can share it with the development to fix it. Because tool should not crash in any ways. 

 

Regarding LUT utilization you may create a new thread with that query. 

Regards,
hemangd

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Visitor
Visitor
610 Views
Registered: ‎02-14-2019

It happens again.

....

INFO: [Common 17-14] Message 'Synth 8-4618' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check '.../synth_1/hs_err_pid7216.log' for details

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Moderator
Moderator
605 Views
Registered: ‎03-16-2017

Hi @mario.niu , 

I have sent you ezmove ftp through which you can provide archived testcase to reproduce this issue at our end and investigate it further.

Regards,
hemangd

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Visitor
Visitor
601 Views
Registered: ‎02-14-2019

sorry, i cannot send you the project.
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Highlighted
Moderator
Moderator
591 Views
Registered: ‎03-16-2017

Hi @mario.niu , 

Can you check with the latest Vivado version 2019.1 ? It might possible that this issue got fixed with this latest version. And you can use your design without any instance modification. 

Regards,
hemangd

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Highlighted
Visitor
Visitor
578 Views
Registered: ‎02-14-2019

I have send you the target file.
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Moderator
Moderator
567 Views
Registered: ‎03-16-2017

hi @mario.niu , 

From the provided RTL file , i am not able to reproduce the issue. Can you provide the full archived project so i can reproduce it. 

(i had removed black box attribute)

Regards,
hemangd

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Visitor
Visitor
554 Views
Registered: ‎02-14-2019

can we find another way to contact for problem?

 

such as video, sharing screen or something else?

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Moderator
Moderator
526 Views
Registered: ‎03-16-2017

Hi @mario.niu , 

Sent you personal message here. 

Regards,
hemangd

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