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amol_aeva
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Registered: ‎01-23-2018

2D Array of System Verilog Interfaces

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I'm using 2017.4 and though UG901 says that Array of Interfaces is Not Supported, I have been successfully using 1D arrays for a while now. 

Example:

bus my_bus[2] ();

 

However when I try to generate a 2D array of interfaces it fails in Elaboration.

bus my_bus[2][2] ();

 

Any idea when this will be supported?

Attached a test case to show this.

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markcurry
Scholar
Scholar
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Registered: ‎09-16-2009

 

Vivado support for multi-dimensional arrays of interfaces is spotty.

 

We've successfully used single dimensional arrays of interfaces with Vivado Synthesis and it's fully supported.  Our designs have had them, and used since one of the 2015 Vivado releases.

 

We are using 2D arrays of interfaces too, but it's limited.

 

Vivado appears to only allow you to index a single (left most, most varying) dimension PER module.  I know that's a bit cryptic.  But Vivado will allow 2-d arrays-of-interface instantiates, and declarations within portlists.  From your examples:

module top()

bus bus2d[3:0][2:0]

submodule sub1 ( .s_bus2d( bus2d ) )

endmodule

module submodule
#( 
  parameter ARRAY1 = 4,
  parameter ARRAY0 = 3
)
(
  bus.s s_bus2d[ ARRAY1 - 1 : 0 ] [ ARRAY0 - 1 : 0 ]
);

generate
  for( genvar i = 0; i < ARRAY1; i++ )
  begin : iter_i
    low_level low_level1( .s_bus1d( s_bus2d[ i ] ) );
  end
endgenerate

endmodule

I left out the low_level module - but it has a 1-d array of interfaces.  Hopefully you get the picture.

 

But Vivado wouldn't let you directly index into both dimensions.  You need to do the "slice" as above to slice off one dimension on it's way down to a lower level.

 

Hopefully that's clear.  It's been on the list of things I wanted to ask Xilinx to address, but lower down for us, since we could work with it like above for our few use cases.

 

Regards,

 

Mark

View solution in original post

5 Replies
markcurry
Scholar
Scholar
6,611 Views
Registered: ‎09-16-2009

 

Vivado support for multi-dimensional arrays of interfaces is spotty.

 

We've successfully used single dimensional arrays of interfaces with Vivado Synthesis and it's fully supported.  Our designs have had them, and used since one of the 2015 Vivado releases.

 

We are using 2D arrays of interfaces too, but it's limited.

 

Vivado appears to only allow you to index a single (left most, most varying) dimension PER module.  I know that's a bit cryptic.  But Vivado will allow 2-d arrays-of-interface instantiates, and declarations within portlists.  From your examples:

module top()

bus bus2d[3:0][2:0]

submodule sub1 ( .s_bus2d( bus2d ) )

endmodule

module submodule
#( 
  parameter ARRAY1 = 4,
  parameter ARRAY0 = 3
)
(
  bus.s s_bus2d[ ARRAY1 - 1 : 0 ] [ ARRAY0 - 1 : 0 ]
);

generate
  for( genvar i = 0; i < ARRAY1; i++ )
  begin : iter_i
    low_level low_level1( .s_bus1d( s_bus2d[ i ] ) );
  end
endgenerate

endmodule

I left out the low_level module - but it has a 1-d array of interfaces.  Hopefully you get the picture.

 

But Vivado wouldn't let you directly index into both dimensions.  You need to do the "slice" as above to slice off one dimension on it's way down to a lower level.

 

Hopefully that's clear.  It's been on the list of things I wanted to ask Xilinx to address, but lower down for us, since we could work with it like above for our few use cases.

 

Regards,

 

Mark

View solution in original post

amol_aeva
Visitor
Visitor
5,529 Views
Registered: ‎01-23-2018

Thanks for the workaround and detailed workaround. I'll try to ask Xilinx to support this - lets see.

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aher
Xilinx Employee
Xilinx Employee
5,504 Views
Registered: ‎07-21-2014
Hi,

While looking into LRM about range specification for array of instances, it says-
"An array of instances shall have a continuous range. One instance identifier shall be associated with only one range to declare an array of instances."

In that case support for 2D array of instance looks like a fallacious request?

-Shreyas
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markcurry
Scholar
Scholar
5,494 Views
Registered: ‎09-16-2009

Firstly, we're talking about an Array of INTERFACES not an array of INSTANCES.

The section you quote is from part of the Verilog spec talking about the latter. 

 

Secondly, the array range is continuous - there's no discontinuity in range.  It's just organized in more than one dimension. 

 

In fact, I'm pretty sure Vivado handles multi-dimensional INSTANCES just fine.  I'm fairly sure I'm using these (without interfaces) in my code today, without issue.

 

EDIT: Just checked - yes we're using this quite -a bit - a multi-dimensional array of INSTANCES - and Vivado handles this just fine in synthesis.

 

It's valid SystemVerilog code to have a multi-dimensional array of interfaces, and should be supported by synthesis.

 

Regards,

 

Mark

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aher
Xilinx Employee
Xilinx Employee
5,232 Views
Registered: ‎07-21-2014

Hi,

 

Sorry for the confusion here. The request of support for multiple dimensional array of interfaces is valid and I filed CR for this issue. It is fixed in next release of tool.

 

-Shreyas 

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Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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